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m4 tk jan . 06 , 201 6 page 1 of 144 rev .1.00 m4tk series datashee t arm ? cortex ? - m 32 - bit microcontroller numicro ? family m4 tk series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvot on.com
m4 tk jan . 06 , 201 6 page 2 of 144 rev .1.00 m4tk series datashee t table of contents 1 general description ................................ ................................ ............................ 8 2 features ................................ ................................ ................................ ................. 10 numicro ? m4tk features ................................ ................................ ................................ .. 10 2.1 3 abbreviations ................................ ................................ ................................ ............... 16 4 parts information list and pin configuration ................................ ........ 18 numicro ? m4tk selection guide ................................ ................................ ....................... 18 4.1 4.1.1 numicro ? m4tk naming rule ................................ ................................ ................................ .......... 18 4.1.2 numicro ? m4tk can series (can+usb) selection guide ................................ ............................. 19 pin configuration ................................ ................................ ................................ ............... 20 4.2 4.2.1 numicro ? m4tk can series (can+usb) lqfp48 pin diagram ................................ .................... 20 4.2.2 numicro ? m4tk can series (can+usb) lqfp64 pin diagram ................................ .................... 21 4.2.3 numicro ? m4tk can series (can+usb) lqfp100 pin diagram ................................ .................. 22 pin description ................................ ................................ ................................ ................... 23 4.3 4.3.1 m4tk can series(can+usb) lqfp48 pin description ................................ ................................ . 23 4.3.2 m4tk can series(can+usb) lqfp64 pin description ................................ ................................ . 30 4.3.3 m4tk can series(can+usb) lqfp100 pin description ................................ ............................... 39 4.3.4 gpio multi - function pin summary ................................ ................................ ................................ ... 51 5 block diagram ................................ ................................ ................................ ....... 60 numicro ? m4tk block diagram ................................ ................................ ......................... 60 5.1 6 functional description ................................ ................................ .................... 61 arm ? cortex ? - m4 core ................................ ................................ ................................ ..... 61 6.1 system manager ................................ ................................ ................................ ................ 64 6.2 6.2.1 overview ................................ ................................ ................................ ................................ ........... 64 6.2.2 system reset ................................ ................................ ................................ ................................ ... 64 6.2.3 power modes and wake - up sources ................................ ................................ ............................... 71 6.2.4 system power distribution ................................ ................................ ................................ ............... 73 6.2.5 system memory map ................................ ................................ ................................ ....................... 75 6.2.6 sram memory organization ................................ ................................ ................................ ............ 78 6.2.7 system timer (systick) ................................ ................................ ................................ ................... 81 6.2.8 nested vectored interrupt controller (nvic) ................................ ................................ ................... 81 clock controller ................................ ................................ ................................ ................. 82 6.3 6.3.1 overview ................................ ................................ ................................ ................................ ........... 82 6.3.2 clock generator ................................ ................................ ................................ ............................... 84 6.3.3 system clock and systick clock ................................ ................................ ................................ ..... 85 6.3.4 peripherals clock ................................ ................................ ................................ ............................. 86
m4 tk jan . 06 , 201 6 page 3 of 144 rev .1.00 m4tk series datashee t 6.3.5 power - down mode clock ................................ ................................ ................................ ................. 87 6.3.6 clock output ................................ ................................ ................................ ................................ ..... 87 flash memeory controller (fmc) ................................ ................................ ....................... 89 6.4 6.4.1 overview ................................ ................................ ................................ ................................ ........... 89 6.4.2 features ................................ ................................ ................................ ................................ ........... 89 external bus interface (ebi) ................................ ................................ ............................... 90 6.5 6.5.1 overview ................................ ................................ ................................ ................................ ........... 90 6.5.2 features ................................ ................................ ................................ ................................ ........... 90 general purpose i/o (gpio) ................................ ................................ .............................. 91 6.6 6.6.1 overview ................................ ................................ ................................ ................................ ........... 91 6.6.2 features ................................ ................................ ................................ ................................ ........... 91 pdma controller (pdma) ................................ ................................ ................................ .. 92 6.7 6.7.1 overview ................................ ................................ ................................ ................................ ........... 92 6.7.2 features ................................ ................................ ................................ ................................ ........... 92 timer controller (tmr) ................................ ................................ ................................ ...... 93 6.8 6.8.1 overview ................................ ................................ ................................ ................................ ........... 93 6.8.2 features ................................ ................................ ................................ ................................ ........... 93 pwm generator and capture timer (pwm) ................................ ................................ ....... 94 6.9 6.9.1 overview ................................ ................................ ................................ ................................ ........... 94 6.9.2 features ................................ ................................ ................................ ................................ ........... 94 watchdog timer (wdt) ................................ ................................ ................................ ..... 96 6.10 6.10.1 overview ................................ ................................ ................................ ................................ ........... 96 6.10.2 features ................................ ................................ ................................ ................................ ........... 96 window watchdog timer (wwdt) ................................ ................................ .................... 97 6.11 6.11.1 overview ................................ ................................ ................................ ................................ ........... 97 6.11.2 featu res ................................ ................................ ................................ ................................ ........... 97 real time clock (rtc) ................................ ................................ ................................ ...... 98 6.12 6.12.1 overview ................................ ................................ ................................ ................................ ........... 98 6.12.2 features ................................ ................................ ................................ ................................ ........... 98 uart interface controller (uart) ................................ ................................ ..................... 99 6.13 6.13.1 overview ................................ ................................ ................................ ................................ ........... 99 6.13.2 features ................................ ................................ ................................ ................................ ........... 99 smart card host interface (sc) ................................ ................................ ....................... 101 6.14 6.14.1 overview ................................ ................................ ................................ ................................ ......... 101 6.14.2 features ................................ ................................ ................................ ................................ ......... 101 i 2 c serial interface controller (i 2 c) ................................ ................................ ................... 102 6.15 6.15.1 overview ................................ ................................ ................................ ................................ ......... 102
m4 tk jan . 06 , 201 6 page 4 of 144 rev .1.00 m4tk series datashee t 6.15.2 features ................................ ................................ ................................ ................................ ......... 102 serial peripheral interface (spi) ................................ ................................ ....................... 103 6.16 6.16.1 overview ................................ ................................ ................................ ................................ ......... 103 6.16.2 features ................................ ................................ ................................ ................................ ......... 103 usb device controller (usbd) ................................ ................................ ........................ 104 6.17 6.17.1 overview ................................ ................................ ................................ ................................ ......... 104 6.17.2 features ................................ ................................ ................................ ................................ ......... 104 usb 1.1 host controller (usbh) ................................ ................................ ...................... 105 6.18 6.18.1 overview ................................ ................................ ................................ ................................ ......... 105 6.18.2 features ................................ ................................ ................................ ................................ ......... 105 usb on - the - go (otg) ................................ ................................ ................................ ... 106 6.19 6.19.1 overview ................................ ................................ ................................ ................................ ......... 106 6.19.2 features ................................ ................................ ................................ ................................ ......... 106 controller area network (can) ................................ ................................ ........................ 107 6.20 6.20.1 overview ................................ ................................ ................................ ................................ ......... 107 6.20.2 features ................................ ................................ ................................ ................................ ......... 107 touch key (tk) ................................ ................................ ................................ ................ 108 6.21 6.21.1 overview ................................ ................................ ................................ ................................ ......... 108 6.21.2 features ................................ ................................ ................................ ................................ ......... 108 crc controller (crc) ................................ ................................ ................................ ...... 109 6.22 6.22.1 overview ................................ ................................ ................................ ................................ ......... 109 6.22.2 features ................................ ................................ ................................ ................................ ......... 109 enhanced 12 - bit analog - to - digital converter (eadc) ................................ ...................... 110 6.23 6.23.1 overview ................................ ................................ ................................ ................................ ......... 110 6.23.2 features ................................ ................................ ................................ ................................ ......... 110 digital to analog converter (dac) ................................ ................................ .................... 111 6.24 6.24.1 overview ................................ ................................ ................................ ................................ ......... 111 6.24.2 features ................................ ................................ ................................ ................................ ......... 111 analog comparator controller (acmp) ................................ ................................ ............ 112 6.25 6.25.1 overview ................................ ................................ ................................ ................................ ......... 112 6.25.2 features ................................ ................................ ................................ ................................ ......... 112 7 application circuit ................................ ................................ ........................... 113 8 electrical characteristics ................................ ................................ .......... 114 absolute maximum ratings ................................ ................................ .............................. 114 8.1 dc electrical characteristics ................................ ................................ ............................ 115 8.2 ac electrical characteristics ................................ ................................ ............................ 121 8.3
m4 tk jan . 06 , 201 6 page 5 of 144 rev .1.00 m4tk series datashee t 8.3.1 external 4~24 mhz high speed crystal (hxt) input clock ................................ ........................... 121 8.3.2 external 4~20 mhz high speed crystal (hxt) oscillator ................................ .............................. 121 8.3.3 22.1184 mhz internal high speed rc oscillator (hirc) ................................ .............................. 122 8.3.4 32.768 khz external low speed crystal (lxt) input clock ................................ .......................... 123 8.3.5 32.768 khz external low speed crystal (lxt) oscillator ................................ ............................. 123 8.3.6 10 khz internal low speed rc oscillator (lirc) ................................ ................................ .......... 124 analog characteristics ................................ ................................ ................................ ..... 125 8.4 8.4.1 12 - bit sar adc ................................ ................................ ................................ .............................. 125 8.4.2 ldo ................................ ................................ ................................ ................................ ................ 127 8.4.3 low voltage reset ................................ ................................ ................................ ......................... 127 8.4.4 brown - out detector ................................ ................................ ................................ ........................ 127 8.4.5 power - on reset ................................ ................................ ................................ .............................. 127 8.4.6 temperature sensor ................................ ................................ ................................ ...................... 128 8.4.7 comparator ................................ ................................ ................................ ................................ ..... 129 8.4.8 12 - bit dac ................................ ................................ ................................ ................................ ...... 129 8.4.9 internal voltage reference ................................ ................................ ................................ ............. 130 8.4.10 usb phy ................................ ................................ ................................ ................................ ........ 130 flash dc electrical characteristics ................................ ................................ .................. 132 8.5 i 2 c dynamic characteristics ................................ ................................ ............................. 133 8.6 spi dynamic characteristics ................................ ................................ ............................ 134 8.7 8.7.1 dynamic characteristics of data input and output pin ................................ ................................ .. 134 i 2 s dynamic characteristics ................................ ................................ ............................. 137 8.8 9 package dimensions ................................ ................................ .......................... 139 lqfp 100l (14x14x1.4 mm footprint 2.0 mm) ................................ ................................ .. 139 9.1 lqfp 64l (10x10x1.4 mm footprint 2.0 mm) ................................ ................................ ... 140 9.2 lqfp 64l (7x7x1.4 mm footprint 2.0 mm) ................................ ................................ ....... 141 9.3 lqfp 48l (7x7x1.4mm footprint 2.0mm) ................................ ................................ ......... 142 9.4 10 revision history ................................ ................................ ................................ . 143
m4 tk jan . 06 , 201 6 page 6 of 144 rev .1.00 m4tk series datashee t list of figures figure 4.1 - 1 numicro ? m4tk selection code ................................ ................................ ................................ .... 18 figure 4.2 - 1 numicro ? m4tk c an series (can+usb) lqfp 48 - pin diagram ................................ ................. 20 figure 4.2 - 2 numicro ? m4tk can series (can+usb) lqfp 64 - pin diagram. ................................ ................ 21 figure 4.2 - 3 numicro ? m4tk can series (can+usb) lqfp 100 - pin diagram. ................................ .............. 22 figure 5.1 - 1 numicro ? m4tk block diagram ................................ ................................ ................................ ..... 60 figure 6.1 - 1 cortex ? - m4 block diagram ................................ ................................ ................................ ............ 61 figure 6.2 - 1 system reset sources ................................ ................................ ................................ .................. 65 figure 6.2 - 2 nreset reset waveform ................................ ................................ ................................ ............. 68 figure 6.2 - 3 power - on reset (por) waveform ................................ ................................ ................................ 68 figure 6.2 - 4 low voltage reset (lvr) waveform ................................ ................................ ............................. 69 figure 6.2 - 5 brown - out detector (bod) waveform ................................ ................................ ........................... 70 figure 6.2 - 6 power mode state machine ................................ ................................ ................................ ........... 71 figure 6.2 - 7 numicro ? m4tk power distribution diagram ................................ ................................ ................ 74 figure 6.2 - 8 sram block diagram ................................ ................................ ................................ .................... 78 figure 6.2 - 9 sram memory organization ................................ ................................ ................................ ......... 79 figure 6.3 - 1 clock generator global view diagram ................................ ................................ .......................... 83 figure 6.3 - 2 clock generator block diagram ................................ ................................ ................................ .... 84 figure 6.3 - 3 system clock block diagram ................................ ................................ ................................ ......... 85 figure 6.3 - 4 hxt stop protect procedure ................................ ................................ ................................ ......... 86 figure 6.3 - 5 systick clock control block diagram ................................ ................................ ........................... 86 figure 6.3 - 6 clock source of clock output ................................ ................................ ................................ ........ 87 figure 6.3 - 7 clock output block diagram ................................ ................................ ................................ .......... 88 figure 8.3 - 1 typical crystal application circuit ................................ ................................ ............................... 122 figure 8.3 - 2 hirc accuracy vs. temperature ................................ ................................ ................................ . 122 figure 8.3 - 3 typical crystal application circuit ................................ ................................ ............................... 124 figure 8.4 - 1 typical connection diagram using the adc ................................ ................................ ................. 12 6 figure 8.4 - 2 power - up ramp condition ................................ ................................ ................................ ........... 128 figure 8.6 - 1 i 2 c timing diagram ................................ ................................ ................................ ...................... 133 figure 8.7 - 1 spi master mode timing diagram ................................ ................................ ............................... 134 figure 8.7 - 2 spi slave mode timing diagram ................................ ................................ ................................ . 136 figure 8.8 - 1 i 2 s master mode timing diagram ................................ ................................ ................................ 138 figure 8.8 - 2 i 2 s slave mode timing diagram ................................ ................................ ................................ .. 138
m4 tk jan . 06 , 201 6 page 7 of 144 rev .1.00 m4tk series datashee t list of tables table 1 - 1 key features support table ................................ ................................ ................................ ................. 8 table 3 - 1 list of abbreviations ................................ ................................ ................................ ........................... 17 table 4 - 1 m4tk gpio multi - function table ................................ ................................ ................................ ....... 59 table 6 - 1 reset value of registers ................................ ................................ ................................ ................... 67 table 6 - 2 power mode difference table ................................ ................................ ................................ ............ 71 table 6 - 3 c lock s in power modes ................................ ................................ ................................ ...................... 73 table 6 - 4 condition of entering power - down mode again ................................ ................................ ................ 73 table 6 - 5 address space assignments for on - chip controllers ................................ ................................ ....... 77 table 6 - 6 numicro ? m4tk s eries uart feature ................................ ................................ ............................ 100
m4 tk jan . 06 , 201 6 page 8 of 144 rev .1.00 m4tk series datashee t 1 general description the m4tk series includes a total of 33 arm ? cortex ? - m4f based products, including the m4tk can serie s which is pin compatible with m051 lqfp48 and m058s lqfp64. by planning a complete product line, nuvoton hopes to fulfill the demand for the arm ? cortex ? - m4f core with products at all levels and realize its customer commitment: total support for long - term competitiveness enhancement, and to fulfill their current product development demand and future innovation imagination. the m4tk series embedded with the arm ? cortex ? - m4f core supports dsc (digital signal controller) and fpu (float point unit) and feature s high performance computing capability running up to 72 mhz, built - in 256/128 k b flash rom, 32/16 k b sram complying with iec60730, built - in boot rom and independent 4 k b in - system programming flash rom for developing more flexible online upgrade code that support external uart, spi, i 2 c, can and usb. it also supports ebi to provide greater flexibility for external memory. the entire m4tk series is provided with outstanding specifications: four 32 - bit timers, dual watchdogs, and integrates plenty of peripher als such as pdma and rtcs, five uarts that support 16 - byte fifo, three sets of spi controllers that support quad mode, two i2c devices that support smbus and pmbus, two sets of i 2 s, two lins, can bus, iso - 7816 - 3 interface, full - speed usb otg, full - speed us b devices, 16 - channel 12 - bit adc with 1 msps conversion rate, built - in reference voltage (v ref ) for circuit generation, 12 - bit dac, two analog comparators and temperature detectors. the m4tk series provides two special designs. one is high - resolution 144 m hz pwm with high - speed electromechanical control timer and resolution<7ns. in conjunction with a driver adc, it delivers hardware brake protection and pulse capture functions to save mcu computing burden and effectively carry out advanced computing require d by motor control, making it exceptionally outstanding in industrial automation and motor control performance. the other is vai (voltage adjustment interface) system to support voltage level adjustment with individual i/o (1.8v - 5.5v) for saving additional cost on adjusting the interface voltage difference of peripheral components. the m4tk series also provides the wide operating voltage (2.5v - 5.5v) and 5v - tolerance input i/o to significantly enhance system stability, industrial operating temperature ( - 40c - 105c), 22.1184 mhz internal rc oscillator (hirc variation < 2%) and 32.768 khz external crystal oscillator to trim hirc (hirc variation < 0.25%) working at - 40?c - 105?c to boost system immunity and adequately fulfill the high precision demand of comm unications. the m4tk series is specifically suitable for high - performance and high - precision applications, such as industrial control, system automation, security surveillance, autotronics and digital power control. product line usb can uart i 2 c i 2 s spi pwm adc dac rtc ebi m4tk table 1 - 1 key features support table the numicro ? m4tk series is suitable for a wide range of applications such as: ? industrial automation ? plcs ? inverters ? home automation ? security alarm system ? power metering ? portable data collector ? portable rfid reader
m4 tk jan . 06 , 201 6 page 9 of 144 rev .1.00 m4tk series datashee t ? system supervisors ? smart card reader ? printer ? bar code scanner ? motor control ? digital power
m4 tk jan . 06 , 201 6 page 10 of 144 rev .1.00 m4tk series datashee t 2 features numicro ? m4tk features 2.1 ? core C arm ? cortex ? - m 4f core run ning up to 72 mhz C supports dsp extension with hardware divider C supports ieee 754 compliant floating - point unit (fpu) C supports memory protection unit (mpu) C one 24 - bit system timer C supports l ow p ower s leep mode by wfi and wfe instructions C single - cycle 32 - bit hardware multiplier C supports programmable 16 level priorities of nested vectored interrupt controller (nvic) C supports programmable mask - able interrupts ? buil t - in ldo for wide operating voltage range d from 2.5v to 5.5v ? flash memory C supports 128/256 k b application rom (aprom) C supports 4 kb flash for loader (ldrom) C supports d ata f lash with configurable memory size C supports in - s ystem - p rogram ming (isp) , in - a pplication - p rogram ming (iap) update embedded flash memory C supports 2 k b page erase for all embedded fla sh ? boot loader C 16 kb embedde d rom C supports nuvoton native in - system - program ming (isp) for uart0, spi0, i 2 c0, can *1 and usb *2 C supports direct boot from boot loader by pin selection ? sram memory C 32 /16 k b embedded sram C 16 /8 kb with hardware parity check C supports byte - , half - word - and word - access C supports exception (nmi) generated once a parity check error occurs C supports pdma mode ? pdma (peripheral dma) C supports 12 /8 independent configurable channels for automatic data transfer between memories and peripherals C sup ports normal and scatter - gather transfer modes C supports two types of priorities modes: fixed - priority and round - robin modes C supports byte - , half - word - and word - access C auto increment of the source and destination address C supports single and burst transfer type ? clock control C built - in 22.1184 mhz i nternal h igh s peed rc o scillator (hirc) f or system operation (variation < 2% at - 40?c ~ +105?c ) C built - in 10 khz internal low speed rc oscillator (lirc) for watchdog timer and wake - up operation C built - in 4~20 mhz external high speed crystal oscillator (hxt) for precise timing operation C built - in 32.768 khz external low speed crystal oscillator (lxt) for rtc function and low - power system operation
m4 tk jan . 06 , 201 6 page 11 of 144 rev .1.00 m4tk series datashee t C supports one pll up to 144 mhz for high performance system operat ion , sourced from hirc and hxt C supports clock failure detection for high/low speed external crystal oscillator C supports exception (nmi) generated once a clock failure detected C supports clock out put ? gpio C four i/o modes C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level trigger setting C supports h igh driver and high sink current i / o (up to 20 ma at 5v) C supports software selectable slew rate control C supports 5v - tolerance function for following pins ? pa.0 ~ pa.15, pc.0 ~ pc.7, pc.9 ~ pc.15, pd.5 ~ pd.8, pd.10 ~ pd.15, pe.0 ~ pe.14, pf.2, pf.5 ~ pf.6 ? pa.0 ~ pa.15, pb.14 ~ pb.14, pc.0 ~ pc.8, pc.10 ~ pc.13, pd.4 ~ pd.7, pd.12 ~ pd.15, pe.0 ~ pe.1, pe.3 ~ pe.5, pe.8 ~ pe.13, pf.2 . C supports up to 85/55/42 gpios for lqfp100/64/ 48 respectively ? timer C supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides o ne - shot, p eriodic, t oggle and continuous c ounting operation modes C supports event counting function to count the event from external pin C supports input capture function to capture or reset counter value ? watchdog timer C supports m ultiple clock sources from lirc (default selection) , hclk/2048 and lxt C 8 selectable time - out period from 1. 6ms ~ 26 .0sec (depend ing on clock source) C able to wake up from power - down or idle mode C interrupt or reset selectable on watchdog time - out ? window watchdog time r C supports m ultiple clock sources from hclk/2048 (default selection) and lirc C window set by 6 - bit counter with 11 - bit prescale C able to wake up from p ower - down or i dle mode C interrupt or reset selectable on t ime - out ? rtc C supports external power pin v bat C supports software compensation by setting frequency compensate register (fcr) C supports rtc counter (second, minute, hour) and calendar counter (day, month, year) C supports alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports wake - up function C supports 80 bytes spare registers C programmable spare register erase function C supports 32k hz oscillator gain control C supports tamper detection function ? pwm C supports up to 12 independent pwm outputs with 16 - bit resolution C supports maximum clock frequency up to 144mhz C supports 12 - bit clock pres c ale C supports one - shot or auto - reload counter operation mode
m4 tk jan . 06 , 201 6 page 12 of 144 rev .1.00 m4tk series datashee t C supports up, down or up - down pwm counter type C supports synchronous function C supports dead time with maximum divided 12 - bit prescale C supports brake function source from pin , comparator output and system safety events C supports p wm auto recovery function after brake condition removed C supports mask function and tri - state output for each pwm pin C supports pwm events i nterrupt C supports trigger e adc /dac start conversion C supports up to 12 independent input c apture channel s with rising/falling capture and with counter reload option C supports c apture counter with 16 - bit resolution C supports capture interrupt C support s capture pdma mode ? uart C supports up to four uarts C uart0, uart1, uart2 and uart3 C supports 16 - byte fifos with programmable level trigger C supports auto flow control ( cts and rts) C supports irda (sir) function C supports rs - 485 9 - bit mode and direction control C uart0 and uart1 support lin function C programmable baud - rate generator up to 1/16 system clock C supports wake - up function C supports pdma mode ? smart card interface C one set of iso - 7816 - 3 port C compliant to iso - 7816 - 3 t=0, t=1 C separate receive / transmit 4 bytes entry fifo for data payloads C programmable transmission clock frequency C programmable receiver buffer trigger level C programmable guard time selection (11 etu ~ 266 etu) C a 24 - bit and two 8 bit time - out counters for answer to request (atr) and waiting times processing C supports auto inverse convention function C supports stop clock level and clock stop (clock keep) function C supports transmitter and receiver error retry and error limit function C supports hardware activation/deactivation sequence process C supports hardware warm reset sequence process C supports hardware auto deactivation sequence when detect the card is removal C supports uart function ? spi C supports one set of spi quad controller C spi0 C supports master or slave mode operation C supports 2 - bit transfer mode C supports dual and quad i/o transfer mode C configurable bit length of a transfer word from 8 to 32 - bit C provides separate 8 - level depth transmit and receive fifo buffers C supports msb first or lsb first transfer sequence C supports the byte reorder function C supports byte or word suspend mode C supports pdma mode C supports 3 - wire d , no slave select signal, bi - direction interface C master up to 32 mhz, and slave up to 16 mhz ( when c hip work s at v dd = 5v) ? spi / i 2 s
m4 tk jan . 06 , 201 6 page 13 of 144 rev .1.00 m4tk series datashee t C supports u p to two sets of spi controllers C spi1 and spi2 C supports master or slave mode operation C configurable bit length of a transfer word from 8 to 32 - bit C provides separate 4 - level depth transmit and receive fifo buffers C supports msb first or lsb first transfer sequence C supports the byte reorder function C supports byte or word suspend mode C supports 3 - wire, no slave select signal, bi - direction interface C master mode up to 3 6 mhz and slave mode up to 18 mhz ( when c hip work s at v dd = 5v) C supports u p to two sets of i 2 s by spi controllers C spi1 and spi2 C interface with external audio codec C supports m aster and s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and stereo audio data C supports pcm mode a, pcm mode b, i 2 s and msb justified data format C each provides t wo 4 - word fifo data buffers , one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C each s upport s two p dma requests, one for transmit ting and the other for receiv ing ? i 2 c C supports u p to two sets of i 2 c device s C supports master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate cont rol C supports multiple address recognition (four slave address with mask option) C supports smbus and pmbus C supports speed up to 1mbps C supports multi - address power - down wake - up function ? can 2.0 C supports up to one set of can controller C supports can protocol version 2.0 part a and b C bit rates up to 1m bit/s C each supports 32 message objects C each message object has its own identifier mask C programmable fifo mode (concatenation of message object) C supports interrupts C disabled automatic re - transmission mode for time triggered can applications C supports p ower - down wake - up function ? usb 2.0 fs controller C supports o ne set of usb 2.0 fs otg C fs host compatible with open hci 1.0 specification C compliant to usb specification version 2.0 C otg compliant with usb otg supplemen t 1.3 C on - chip usb transceiver C supports control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms
m4 tk jan . 06 , 201 6 page 14 of 144 rev .1.00 m4tk series datashee t C provide s 8 programmable endpoints C supports 512 bytes internal sram as usb buffer C provide s remote wake - up capability C on - chip 5v to 3.3v ldo for usb phy ? ebi C supports two dedicated external chip select pins for each memory block C supports a ccessible space up to 1 m b for each bank, actual ly external addressable space is depend ent on package pin out C supports 8 - /16 - bit data width C supports byte write in 16 - bit data width mode C supports pdma mode C supports address/data m ultiplexed mode C supports timing parameters individual adjustment for each memory block ? e adc C analog input voltage range: 0~ v ref (max to a v dd ) C supports single 12 - bit sar adc conversion C 12 - bit resolution and 10 - bit accuracy is guaranteed C u p to 1m sps conversion rate at 5.0v C up to 16 external single - ended analog input channels C up to 8 differential analog input pairs C supports single adc interrupt C supports e xternal v ref pin C support internal reference voltages from band - gap and voltage divider C an a/d conversion can be triggered by software enable, external pin, timer 0~3 overflow pulse trigger and pwm trigger C supports 3 internal channels for v bat , band - gap vbg input and temperature sensor input C supports pdma transfer ? dac C supports a 12 - bit voltage type dac C rail to rail settle time 8us C external reference voltage v ref C max. output voltage av dd - 0.2v at buffer mode C conversion started by software enable or pdma trigger C support s pdma m ode ? touch key C supports up to 16 touch keys C supports p rogrammable sensitivity adjustment for each channel C supports p rogrammable scan speed for different applications C supports any key w ake - up for low - power applications C support s manual/one - time or periodic key - scan initiation C supports programmable interrupt options for automatic key - scan and interrupt generation ? analog comparator C u p to two rail - to - rail analog comparator s C supports a multiplexed i/o pin at positive node. C supports i/o pins, band - gap , voltage divider and dac output at negative node C supports programmable speed and power consumption C interrupt s generated when compare result s change (interrupt event condition is programmable) C supports power - down w ake - up C supports triggers for break events and cycle - by - cycle control for pwm
m4 tk jan . 06 , 201 6 page 15 of 144 rev .1.00 m4tk series datashee t ? cyclic redundancy calculation unit C supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 C programmable initial value C supports programmable order reverse setting for inp ut data and crc checksum C supports programmable 1s complement setting for input data and crc checksum. C supports 8 - /16 - /32 - bit of data width C interrupt generated once checksum error occurs ? voltage adjustable interface C supports user configurable 1.8 ~5.5 v i / o i nterface with a dedicated power input (v ddio ) C supports uart1, spi0, spi1, i 2 c1 or i 2 c0 interface ? supports 96 - bit unique id (uid) ? supports 128 - bit unique customer id (ucid) ? one built - in t emperature sensor with 1 resolution ? brown - o ut detector C with 4 levels: 4. 4 v/ 3. 7 v/ 2.7 v/ 2.2 v C supports brown - o ut interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0 v ? operating temperature: - 40 ~105 ? packages C all green package ( ro hs ) C lqfp 100 - pin (1 4 mm x 1 4 mm) C lqfp 64 - pin (10mm x 10mm) C lqfp 64 - pin (7mm x 7mm) C lqfp 48 - pin ( 7 mm x 7 mm) note: *1: for optional part numbers which support can *2: for optional part numbers which support usb
m4 tk jan . 06 , 201 6 page 16 of 144 rev .1.00 m4tk series datashee t 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection can controller area network dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~20 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sd secure digital spi serial peripheral interface
m4 tk jan . 06 , 201 6 page 17 of 144 rev .1.00 m4tk series datashee t sps samples per second tdes triple data encryption standard tk touch key tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3 - 1 list of abbreviations
m4 tk jan . 06 , 201 6 page 18 of 144 rev .1.00 m4tk series datashee t 4 parts information li st and pin configura tion numicro ? m4tk selection guide 4.1 4.1.1 numicro ? m4tk naming rule figure 4.1 - 1 numicro ? m4tk selection code in this document, m4tk x g means the part numbers which include 256 kb flash, m4tk x e means the part numbers which include 128 kb flash . m 4 t k - x x x x x a r m C c o r t e ? - m 4 t k : t o u c h k e y f l a s h r o m e : 1 2 8 k b g : 2 5 6 k b t e m p e r a t u r e r e s e r v e d s r a m s i z e 3 : 1 6 k b 6 : 3 2 k b p a c k a g e t y p e l : l q f p 4 8 7 x 7 m m s : l q f p 6 4 7 x 7 m m r : l q f p 6 4 1 0 x 1 0 m m v : l q f p 1 0 0 1 4 x 1 4 m m e : - 4 0 o c ~ + 1 0 5 o c
m4 tk jan . 06 , 201 6 page 19 of 144 rev .1.00 m4tk series datashee t 4.1.2 numicro ? m4tk can series (can+usb) selection guide part number flash (kb) sram (kb) isp loader rom (kb) i/o timer connectivity i 2 s usb pwm analog comp. dac (12 - bit) adc (12 - bit) touch key rtc ebi icp / ispi / ap package uart * sc * (iso - 7816 ) spi i 2 c can lin m4tk l g 6a e 256 32 4 34 4 3 +1 1 3 2 2 2 otg 1 0 2 1 8 - ch 6 lqfp 48 m4tk le6ae 128 32 4 34 4 3 +1 1 3 2 2 2 otg 1 0 2 1 8 - ch 6 lqfp 48 m4tk rg6a e 256 32 4 48 4 4 +1 1 3 2 2 2 otg 12 2 1 12 - ch 1 1 lqfp 64 m4tk re6a e 128 32 4 48 4 4 +1 1 3 2 2 2 otg 12 2 1 12 - ch 1 1 lqfp 64 m4tk vg6a e 256 32 4 8 0 4 4 +1 1 3 2 2 2 otg 12 2 1 16 - ch 16 lqfp 100 m4tk ve6ae 128 32 4 8 0 4 4 +1 1 3 2 2 2 otg 12 2 1 16 - ch 16 lqfp 100 * marked in this table (4+1) means 4 uart + 1 sc uart *sc (iso - 7816) supports full duplex uart mode
m4 tk jan . 06 , 201 6 page 20 of 144 rev .1.00 m4tk series datashee t pin configuration 4.2 4.2.1 numicro ? m4tk can series ( can+usb) lqfp 48 p in diagram corresponding part number: m4tk lg6ae, m4tk le6ae figure 4.2 - 1 numicro ? m4tk can series ( can+usb) lqfp 48 - pin diagram n r e s e t a v s s x 3 2 _ o u t / p f . 0 x 3 2 _ i n / p f . 1 v d d v r e f v d d i o p e . 1 3 ( l v i o ) p e . 1 2 ( l v i o ) p e . 1 1 ( l v i o ) p a . 3 p c . 1 p c . 0 l d o _ c a p v s s p f . 4 / x t 1 _ i n p f . 3 / x t 1 _ o u t p d . 7 p f . 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 p e . 1 0 ( l v i o ) l q f p 4 8 - p i n p d . 2 p d . 3 v b a t p e . 0 p c . 4 p c . 3 p c . 2 2 6 2 7 2 8 2 9 3 0 3 1 3 2 p f . 6 / i c e _ d a t p f . 5 / i c e _ c l k 4 0 3 9 3 8 3 7 p a . 2 p a . 1 p a . 0 2 5 a v d d u s b _ d + u s b _ d - u s b _ v b u s u s b _ v d d 3 3 _ c a p u s b _ i d p b . 0 p b . 1 p b . 2 p b . 3 p b . 4 p b . 5 p b . 6 p b . 7 p d . 0 p d . 1
m4 tk jan . 06 , 201 6 page 21 of 144 rev .1.00 m4tk series datashee t 4.2.2 numicro ? m4tk can series ( can+usb) lqfp 64 p in diagram corresponding part number: m4tk rg6ae, m4tk re6ae figure 4.2 - 2 numicro ? m4tk can series ( can+usb) lqfp 64 - pin diagram . p b . 5 p b . 6 p b . 7 p d . 0 n r e s e t a v s s v b a t x 3 2 _ o u t / p f . 0 x 3 2 _ i n / p f . 1 p f . 2 v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 1 2 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 ( l v i o ) p e . 1 2 ( l v i o ) p e . 9 ( l v i o ) p e . 8 ( l v i o ) p a . 3 p b . 4 p b . 8 p b . 1 1 p c . 1 p c . 0 l d o _ c a p v d d v s s p f . 4 / x t 1 _ i n p f . 3 / x t 1 _ o u t p d . 7 p d . 1 5 p d . 1 4 p d . 1 3 p d . 1 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 l q f p 6 4 - p i n p b . 1 5 p d . 8 p d . 9 p d . 1 p d . 2 p d . 3 p c . 5 p c . 4 p c . 3 p c . 2 p e . 1 1 ( l v i o ) p e . 1 0 ( l v i o ) p f . 6 / i c e _ d a t p f . 5 / i c e _ c l k p c . 7 p c . 6 p a . 2 p a . 1 p a . 0 v s s u s b _ v d d 3 3 _ c a p u s b _ i d
m4 tk jan . 06 , 201 6 page 22 of 144 rev .1.00 m4tk series datashee t 4.2.3 numicro ? m4tk can series (can+usb) lqfp100 p in diagram corresponding part number: m4tk vg6ae, m4tk ve6ae figure 4.2 - 3 numicro ? m4tk can series (can+usb) lqfp 100 - pin diagram . u s b _ i d u s b _ v d d 3 3 _ c a p p e . 2 p b . 5 p b . 6 p b . 7 p d . 0 n r e s e t a v s s v d d v s s p c . 8 p d . 5 p e . 3 p d . 6 v b a t x 3 2 _ o u t / p f . 0 x 3 2 _ i n / p f . 1 p f . 2 p a . 1 5 v d d a v d d v r e f p b . 0 p b . 1 p b . 2 p b . 3 p b . 1 2 u s b _ d + u s b _ d - u s b _ v b u s v d d i o p e . 1 3 ( l v i o ) p e . 1 2 ( l v i o ) p e . 9 ( l v i o ) p e . 8 ( l v i o ) p e . 1 v d d v s s p a . 4 p a . 5 p a . 6 p a . 3 p b . 4 p b . 8 p b . 1 1 p c . 1 p c . 0 p c . 1 4 p c . 1 3 p c . 1 0 p c . 9 l d o _ c a p v d d v s s p f . 4 / x t 1 _ i n p f . 3 / x t 1 _ o u t p d . 7 p d . 1 5 p d . 1 4 p d . 1 3 p d . 1 2 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p a . 7 p a . 9 l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p b . 1 3 p b . 1 4 p b . 1 5 p d . 8 p d . 9 p d . 1 p d . 2 p d . 3 p d . 4 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p d . 1 1 p d . 1 0 p c . 1 2 p c . 1 1 p c . 5 p e . 0 p c . 4 p c . 3 p c . 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 p e . 1 1 ( l v i o ) p e . 1 0 ( l v i o ) p a . 8 p f . 6 / i c e _ d a t p f . 5 / i c e _ c l k p e . 5 p e . 4 p c . 7 p c . 6 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p b . 9 p b . 1 0 p a . 2 p a . 1 p a . 0 p a . 1 2 p a . 1 3 p a . 1 4 v s s
m4 tk jan . 06 , 201 6 page 23 of 144 rev .1.00 m4tk series datashee t pin description 4.3 4.3.1 m4tk can series(can+usb) lqfp 48 pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[3:0]=0x0. pa.9 mfp5 means sys_gpa_mfph[7:4]=0x5. pin no . pin name type mfp * description 1 pb.5 i/o mfp0 general purpose digital i/o pin. eadc_ch13 a mfp1 e adc analog input channel 13. spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. spi1_mosi i/o mfp3 spi1 mosi (master out, slave in) pin. tk3 a mfp4 touch key3 . acmp0_p2 a mfp5 comparator0 positive input pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. 2 pb.6 i/o mfp0 general purpose digital i/o pin. eadc_ch14 a mfp1 e adc analog input channel 14. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. tk4 a mfp4 touch key4 . acmp0_p1 a mfp5 comparator0 positive input pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 3 pb.7 i/o mfp0 general purpose digital i/o pin. eadc_ch15 a mfp1 e adc analog input channel 15. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin tk5 a mfp4 touch key5 . acmp0_p0 a mfp5 comparator0 positive input pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 4 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 5 pd.0 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk o mfp2 i2s1 master clock output pin. uart0_rxd i mfp3 data receiver input pin for uart0. tk6 a mfp4 touch key6 . acmp1_n a mfp5 comparator1 negative input pin. int3 i mfp8 external interrupt3 input pin. 6 av ss p mfp0 ground pin for analog circuit.
m4 tk jan . 06 , 201 6 page 24 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 7 pd.1 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp2 pwm 0 counter synchronous trigger input pin. uart0_txd o mfp3 data transmitter output pin for uart0. tk10 a mfp4 touch key10 . acmp1_p2 a mfp5 comparator1 positive input pin. t0 i/o mfp6 timer0event counter input / toggle output ebi_nrd o mfp7 ebi read enable output pin. 8 pd.2 i/o mfp0 general purpose digital i/o pin. stadc i mfp1 adc external trigger input. t0_ext i mfp3 timer0 external capture input . tk11 a mfp4 touch key11 . acmp1_p1 a mfp5 comparator1 positive input pin. pwm0_brake0 i mfp6 pwm0 break input 0 ebi_nwr o mfp7 ebi write enable output pin. int0 i mfp8 external interrupt0 input pin. 9 pd.3 i/o mfp0 general purpose digital i/o pin. t2 i/o mfp1 timer2 event counter input / toggle output t1_ext i mfp3 timer1 external capture input tk12 a mfp4 touch key12 . acmp1_p0 a mfp5 comparator1 positive input pin. pwm0_brake1 i mfp6 pwm0 break input 1 ebi_mclk o mfp7 ebi external clock output pin int1 i mfp8 external interrupt1 input pin. 10 v bat mfp0 power supply by batteries for rtc and pf.0~pf.2 . 11 pf.0 i/o mfp0 general purpose digital i/o pin. x32_out o mfp1 external 32.768 khz (low speed) crystal output pin. int5 i mfp8 external interrupt5 input pin. 12 pf.1 i/o mfp0 general purpose digital i/o pin. x32_in i mfp1 external 32.768 khz (low speed) crystal input pin. 13 pf.2 i/o mfp0 general purpose digital i/o pin. tamper i/o mfp1 tamper detector loop pin 14 pd.7 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp3 pwm 0 counter synchronous trigger input pin. t1 i/o mfp4 timer1 event counter input / toggle output
m4 tk jan . 06 , 201 6 page 25 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description acmp0_o o mfp5 comparator0 output . pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_nrd o mfp7 ebi read enable output pin. 15 pf.3 i/o mfp0 general purpose digital i/o pin. xt1_out o mfp1 external 4~20 mhz (high speed) crystal output pin. i2c1_scl i/o mfp3 i2c1 clock pin. 16 pf.4 i/o mfp0 general purpose digital i/o pin. xt1_in i mfp1 external 4~20 mhz (high speed) crystal input pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. 17 v ss a mfp0 ground pin for digital circuit. 18 ldo_cap a mfp0 ldo output pin. note: this pin needs to be connected with a 1uf capacitor. 19 pc.0 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. uart2_ncts i mfp3 clear to send input pin for uart2. can0_txd i mfp4 can bus transmitter input. pwm0_ch0 i/o mfp6 pwm0 output/capture input. ebi_ad8 i/o mfp7 ebi address/data bus bit 8. int2 i mfp8 external interrupt2 input pin. 20 pc.1 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out stdac i mfp2 dac external trigger input. uart2_nrts o mfp3 request to send output pin for uart2. can0_rxd i mfp4 can bus receiver input. pwm0_ch1 i/o mfp6 pwm0 output/capture input. ebi_ad9 i/o mfp7 ebi address/data bus bit 9. 21 pc.2 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. uart2_txd o mfp3 data transmitter output pin for uart2. acmp1_o o mfp5 comparator1 output . pwm0_ch2 i/o mfp6 pwm0 output/capture input. ebi_ad10 i/o mfp7 ebi address/data bus bit 10. 22 pc.3 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin.
m4 tk jan . 06 , 201 6 page 26 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description uart2_rxd i mfp3 data receiver input pin for uart2. usb_v bus _st i mfp4 usb external vbus regulator status pin. pwm0_ch3 i/o mfp6 pwm0 output/capture input. ebi_ad11 i/o mfp7 ebi address/data bus bit 11. 23 pc.4 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i2c1 clock pin. usb_v bus _en o mfp4 usb external vbus regulator enable pin. pwm0_ch4 i/o mfp6 pwm0 output/capture input. ebi_ad12 i/o mfp7 ebi address/data bus bit 12. 24 pe.0 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. t2_ext i mfp4 timer2 external capture input sc0_cd i mfp5 smartcard card detect pin. pwm0_ch0 i/o mfp6 pwm0 output/capture input. ebi_ncs1 o mfp7 ebi chip select 1 enable output pin. int4 i mfp8 external interrupt4 input pin. 25 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin 26 pf.6 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin 27 pe.10 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp1 spi1 miso (master in, slave out) pin. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. uart1_ncts i mfp3 clear to send input pin for uart1. i2c0_smbal o mfp4 i2c0 smbus smbalter# pin sc0_dat i/o mfp5 smartcard data pin. 28 pe.11 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp1 spi1 mosi (master out, slave in) pin. spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. uart1_nrts o mfp3 request to send output pin for uart1. i2c0_smbsus o mfp4 i2c0 smbus smbsus# pin (pmbus control pin) sc0_clk o mfp5 smartcard clock pin.
m4 tk jan . 06 , 201 6 page 27 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 29 pe.12 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp1 spi1 slave select pin spi0_ss i/o mfp2 spi0 slave select pin. uart1_txd o mfp3 data transmitter output pin for uart1. i2c0_scl i/o mfp4 i2c0 clock pin. 30 pe.13 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp1 spi1 serial clock pin spi0_clk i/o mfp2 spi0 serial clock pin. uart1_rxd i mfp3 data receiver input pin for uart1. i2c0_sda i/o mfp4 i2c0 data input/output pin. 31 v dd io a mfp0 power supply for pe.10~pe.13 . 32 usb_vbus a mfp0 power supply from usb* host or hub. 33 usb_d - i mfp0 usb differential signal d - . 34 usb_d+ i mfp0 usb differential signal d+. usb_id i mfp0 usb identification. 36 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. note: this pin needs to be connected with a 1uf capacitor. 37 pa.3 i/o mfp0 general purpose digital i/o pin. usb_v bus _st i mfp1 usb external vbus regulator status pin. uart0_rxd i mfp2 data receiver input pin for uart0. uart0_nrts o mfp3 request to send output pin for uart0. i2c0_scl i/o mfp4 i2c0 clock pin. sc0_pwr o mfp5 smartcard power pin. pwm1_ch2 i/o mfp6 pwm1 output/capture input. ebi_ad3 i/o mfp7 ebi address/data bus bit 3. 38 pa.2 i/o mfp0 general purpose digital i/o pin. usb_v bus _en o mfp1 usb external vbus regulator enable pin. uart0_txd o mfp2 data transmitter output pin for uart0. uart0_ncts i mfp3 clear to send input pin for uart0. i2c0_sda i/o mfp4 i2c0 data input/output pin. sc0_rst o mfp5 smartcard reset pin. pwm1_ch3 i/o mfp6 pwm1 output/capture input. ebi_ad2 i/o mfp7 ebi address/data bus bit 2. 39 pa.1 i/o mfp0 general purpose digital i/o pin.
m4 tk jan . 06 , 201 6 page 28 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description uart1_nrts o mfp1 request to send output pin for uart1. uart1_rxd i mfp3 data receiver input pin for uart1. can0_txd i mfp4 can bus transmitter input. sc0_dat i/o mfp5 smartcard data pin. pwm1_ch4 i/o mfp6 pwm1 output/capture input. ebi_ad1 i/o mfp7 ebi address/data bus bit 1. 40 pa.0 i/o mfp0 general purpose digital i/o pin. uart1_ncts i mfp1 clear to send input pin for uart1. uart1_txd o mfp3 data transmitter output pin for uart1. can0_rxd i mfp4 can bus receiver input. sc0_clk o mfp5 smartcard clock pin. pwm1_ch5 i/o mfp6 pwm1 output/capture input. ebi_ad0 i/o mfp7 ebi address/data bus bit 0. int0 i mfp8 external interrupt0 input pin. 41 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 42 av dd a mfp0 power supply for internal analog circuit. 43 v ref i mfp0 voltage reference input for adc. note: this pin needs to be connected with a 1uf capacitor. 44 pb.0 i/o mfp0 general purpose digital i/o pin. eadc_ch0 a mfp1 eadc analog input. spi0_mosi1 i/o mfp2 spi0 2nd mosi (master out, slave in) pin. uart2_rxd i mfp3 data receiver input pin for uart2. t2 i/o mfp4 timer2 event counter input / toggle output dac a mfp5 dac analog output ebi_nwrl o mfp7 ebi low byte write enable output pin. int1 i mfp8 external interrupt1 input pin. 45 pb.1 i/o mfp0 general purpose digital i/o pin. eadc_ch1 a mfp1 e adc analog input channel 1. spi0_miso1 i/o mfp2 spi0 2nd miso (master in, slave out) pin. uart2_txd o mfp3 data transmitter output pin for uart2. t3 i/o mfp4 timer3 event counter input / toggle output sc0_rst o mfp5 smartcard reset pin. pwm0_sync_out o mfp6 pwm 0 counter synchronous trigger output pin. ebi_nwrh o mfp7 ebi high byte write enable output pin
m4 tk jan . 06 , 201 6 page 29 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 46 pb.2 i/o mfp0 general purpose digital i/o pin. eadc_ch2 a mfp1 e adc analog input channel 2. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin uart1_rxd i mfp4 data receiver input pin for uart1. sc0_cd i mfp5 smartcard card detect pin. 47 pb.3 i/o mfp0 general purpose digital i/o pin. eadc_ch3 a mfp1 e adc analog input channel 3. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. uart1_txd o mfp4 data transmitter output pin for uart1. 48 pb.4 i/o mfp0 general purpose digital i/o pin. eadc_ch4 a mfp1 e adc analog input channel 4. spi0_ss i/o mfp2 spi0 slave select pin. spi1_ss i/o mfp3 spi1 slave select pin uart1_ncts i mfp4 clear to send input pin for uart1. acmp0_n a mfp5 comparator0 negative input pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7.
m4 tk jan . 06 , 201 6 page 30 of 144 rev .1.00 m4tk series datashee t 4.3.2 m4tk can series(can+usb) lqfp 64 pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[3:0]=0x0. pa.9 mfp5 means sys_gpa_mfph[7:4]=0x5. pin no . pin name type mfp * description 1 pb.15 i/o mfp0 general purpose digital i/o pin. eadc_ch12 a mfp1 e adc analog input channel 12. tk2 a mfp4 touch key2. acmp0_p3 a mfp5 comparator0 positive input pin. ebi_ncs1 o mfp7 ebi chip select 1 enable output pin. 2 pb.5 i/o mfp0 general purpose digital i/o pin. eadc_ch13 a mfp1 e adc analog input channel 13. spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. spi1_mosi i/o mfp3 spi1 mosi (master out, slave in) pin. tk3 a mfp4 touch key3 . acmp0_p2 a mfp5 comparator0 positive input pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. 3 pb.6 i/o mfp0 general purpose digital i/o pin. eadc_ch14 a mfp1 e adc analog input channel 14. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. tk4 a mfp4 touch key4 . acmp0_p1 a mfp5 comparator0 positive input pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 4 pb.7 i/o mfp0 general purpose digital i/o pin. eadc_ch15 a mfp1 e adc analog input channel 15. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin tk5 a mfp4 touch key5 . acmp0_p0 a mfp5 comparator0 positive input pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 5 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 6 pd.0 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk o mfp2 i2s1 master clock output pin. uart0_rxd i mfp3 data receiver input pin for uart0.
m4 tk jan . 06 , 201 6 page 31 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description tk6 a mfp4 touch key6 . acmp1_n a mfp5 comparator1 negative input pin. int3 i mfp8 external interrupt3 input pin. 7 av ss p mfp0 ground pin for analog circuit. 8 pd.8 i/o mfp0 general purpose digital i/o pin. tk8 a mfp4 touch key0 . ebi_ncs0 o mfp7 ebi chip select 0 enable output pin. 9 pd.9 i/o mfp0 general purpose digital i/o pin. tk9 a mfp4 touch key8 . acmp1_p3 a mfp5 comparator1 positive input pin. ebi_ale o mfp7 ebi address latch enable output pin. 10 pd.1 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp2 pwm 0 counter synchronous trigger input pin. uart0_txd o mfp3 data transmitter output pin for uart0. tk10 a mfp4 touch key10 . acmp1_p2 a mfp5 comparator1 positive input pin. t0 i/o mfp6 timer0event counter input / toggle output ebi_nrd o mfp7 ebi read enable output pin. 11 pd.2 i/o mfp0 general purpose digital i/o pin. stadc i mfp1 adc external trigger input. t0_ext i mfp3 timer0 external capture input . tk11 a mfp4 touch key11 . acmp1_p1 a mfp5 comparator1 positive input pin. pwm0_brake0 i mfp6 pwm0 break input 0 ebi_nwr o mfp7 ebi write enable output pin. int0 i mfp8 external interrupt0 input pin. 12 pd.3 i/o mfp0 general purpose digital i/o pin. t2 i/o mfp1 timer2 event counter input / toggle output t1_ext i mfp3 timer1 external capture input tk12 a mfp4 touch key12 . acmp1_p0 a mfp5 comparator1 positive input pin. pwm0_brake1 i mfp6 pwm0 break input 1 ebi_mclk o mfp7 ebi external clock output pin int1 i mfp8 external interrupt1 input pin.
m4 tk jan . 06 , 201 6 page 32 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 13 v bat mfp0 power supply by batteries for rtc and pf.0~pf.2 . 14 pf.0 i/o mfp0 general purpose digital i/o pin. x32_out o mfp1 external 32.768 khz (low speed) crystal output pin. int5 i mfp8 external interrupt5 input pin. 15 pf.1 i/o mfp0 general purpose digital i/o pin. x32_in i mfp1 external 32.768 khz (low speed) crystal input pin. 16 pf.2 i/o mfp0 general purpose digital i/o pin. tamper i/o mfp1 tamper detector loop pin 17 pd.12 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. uart3_txd o mfp3 data transmitter output pin for uart3. pwm1_ch0 i/o mfp6 pwm1 output/capture input. ebi_adr16 o mfp7 ebi address bus bit 16. 18 pd.13 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin. uart3_rxd i mfp3 data receiver input pin for uart3. pwm1_ch1 i/o mfp6 pwm1 output/capture input. ebi_adr17 o mfp7 ebi address bus bit 17. 19 pd.14 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. uart3_ncts i mfp3 clear to send input pin for uart3. pwm1_ch2 i/o mfp6 pwm1 output/capture input. ebi_adr18 o mfp7 ebi address bus bit 18. 20 pd.15 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. uart3_nrts o mfp3 request to send output pin for uart3. pwm1_ch3 i/o mfp6 pwm1 output/capture input. ebi_adr19 o mfp7 ebi address bus bit 19. 21 pd.7 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp3 pwm 0 counter synchronous trigger input pin. t1 i/o mfp4 timer1 event counter input / toggle output acmp0_o o mfp5 comparato r0 output . pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_nrd o mfp7 ebi read enable output pin.
m4 tk jan . 06 , 201 6 page 33 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 22 pf.3 i/o mfp0 general purpose digital i/o pin. xt1_out o mfp1 external 4~20 mhz (high speed) crystal output pin. i2c1_scl i/o mfp3 i2c1 clock pin. 23 pf.4 i/o mfp0 general purpose digital i/o pin. xt1_in i mfp1 external 4~20 mhz (high speed) crystal input pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. 24 v ss a mfp0 ground pin for digital circuit. 25 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 26 ldo_cap a mfp0 ldo output pin. note: this pin needs to be connected with a 1uf capacitor. 27 pc.0 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. uart2_ncts i mfp3 clear to send input pin for uart2. can0_txd i mfp4 can bus transmitter input. pwm0_ch0 i/o mfp6 pwm0 output/capture input. ebi_ad8 i/o mfp7 ebi address/data bus bit 8. int2 i mfp8 external interrupt2 input pin. 28 pc.1 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out stdac i mfp2 dac external trigger input. uart2_nrts o mfp3 request to send output pin for uart2. can0_rxd i mfp4 can bus receiver input. pwm0_ch1 i/o mfp6 pwm0 output/capture input. ebi_ad9 i/o mfp7 ebi address/data bus bit 9. 29 pc.2 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. uart2_txd o mfp3 data transmitter output pin for uart2. acmp1_o o mfp5 comparator1 output . pwm0_ch2 i/o mfp6 pwm0 output/capture input. ebi_ad10 i/o mfp7 ebi address/data bus bit 10. 30 pc.3 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin. uart2_rxd i mfp3 data receiver input pin for uart2. usb_v bus _st i mfp4 usb external vbus regulator status pin.
m4 tk jan . 06 , 201 6 page 34 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description pwm0_ch3 i/o mfp6 pwm0 output/capture input. ebi_ad11 i/o mfp7 ebi address/data bus bit 11. 31 pc.4 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i2c1 clock pin. usb_v bus _en o mfp4 usb external vbus regulator enable pin. pwm0_ch4 i/o mfp6 pwm0 output/capture input. ebi_ad12 i/o mfp7 ebi address/data bus bit 12. 32 pc.5 i/o mfp0 general purpose digital i/o pin. spi2_i2smclk o mfp2 i2s2 master clock output pin . pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_ad13 i/o mfp7 ebi address/data bus bit 13. 33 pc.6 i/o mfp0 general purpose digital i/o pin. i2c1_smbal o mfp3 i2c1 smbus smbalter# pin acmp1_o o mfp5 comparator1 output . pwm1_ch0 i/o mfp6 pwm1 output/capture input. ebi_ad14 i/o mfp7 ebi address/data bus bit 14. 34 pc.7 i/o mfp0 general purpose digital i/o pin. i2c1_smbsus o mfp3 i2c1 smbus smbsus# pin (pmbus control pin) pwm1_ch1 i/o mfp6 pwm1 output/capture input. ebi_ad15 i/o mfp7 ebi address/data bus bit 15. 35 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin 36 pf.6 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin 37 pe.8 i/o mfp0 general purpose digital i/o pin. uart1_txd o mfp1 data transmitter output pin for uart1. spi0_miso1 i/o mfp2 spi0 2nd miso (master in, slave out) pin. i2c1_scl i/o mfp4 i2c1 clock pin. sc0_pwr o mfp5 smartcard power pin. 38 pe.9 i/o mfp0 general purpose digital i/o pin. uart1_rxd i mfp1 data receiver input pin for uart1. spi0_mosi1 i/o mfp2 spi0 2nd mosi (master out, slave in) pin. i2c1_sda i/o mfp4 i2c1 data input/output pin.
m4 tk jan . 06 , 201 6 page 35 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description sc0_rst o mfp5 smartcard reset pin. 39 pe.10 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp1 spi1 miso (master in, slave out) pin. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. uart1_ncts i mfp3 clear to send input pin for uart1. i2c0_smbal o mfp4 i2c0 smbus smbalter# pin sc0_dat i/o mfp5 smartcard data pin. 40 pe.11 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp1 spi1 mosi (master out, slave in) pin. spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. uart1_nrts o mfp3 request to send output pin for uart1. i2c0_smbsus o mfp4 i2c0 smbus smbsus# pin (pmbus control pin) sc0_clk o mfp5 smartcard clock pin. 41 pe.12 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp1 spi1 slave select pin spi0_ss i/o mfp2 spi0 slave select pin. uart1_txd o mfp3 data transmitter output pin for uart1. i2c0_scl i/o mfp4 i2c0 clock pin. 42 pe.13 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp1 spi1 serial clock pin spi0_clk i/o mfp2 spi0 serial clock pin. uart1_rxd i mfp3 data receiver input pin for uart1. i2c0_sda i/o mfp4 i2c0 data input/output pin. 43 v dd io a mfp0 power supply for pe.8~pe.13 . 44 usb_vbus a mfp0 power supply from usb* host or hub. 45 usb_d - i mfp0 usb differential signal d - . 46 usb_d+ i mfp0 usb differential signal d+. usb_id i mfp0 usb identification . 48 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. note: this pin needs to be connected with a 1uf capacitor. 49 pa.3 i/o mfp0 general purpose digital i/o pin. usb_v bus _st i mfp1 usb external vbus regulator status pin. uart0_rxd i mfp2 data receiver input pin for uart0. uart0_nrts o mfp3 request to send output pin for uart0.
m4 tk jan . 06 , 201 6 page 36 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description i2c0_scl i/o mfp4 i2c0 clock pin. sc0_pwr o mfp5 smartcard power pin. pwm1_ch2 i/o mfp6 pwm1 output/capture input. ebi_ad3 i/o mfp7 ebi address/data bus bit 3. 50 pa.2 i/o mfp0 general purpose digital i/o pin. usb_v bus _en o mfp1 usb external vbus regulator enable pin. uart0_txd o mfp2 data transmitter output pin for uart0. uart0_ncts i mfp3 clear to send input pin for uart0. i2c0_sda i/o mfp4 i2c0 data input/output pin. sc0_rst o mfp5 smartcard reset pin. pwm1_ch3 i/o mfp6 pwm1 output/capture input. ebi_ad2 i/o mfp7 ebi address/data bus bit 2. 51 pa.1 i/o mfp0 general purpose digital i/o pin. uart1_nrts o mfp1 request to send output pin for uart1. uart1_rxd i mfp3 data receiver input pin for uart1. can0_txd i mfp4 can bus transmitter input. sc0_dat i/o mfp5 smartcard data pin. pwm1_ch4 i/o mfp6 pwm1 output/capture input. ebi_ad1 i/o mfp7 ebi address/data bus bit 1. 52 pa.0 i/o mfp0 general purpose digital i/o pin. uart1_ncts i mfp1 clear to send input pin for uart1. uart1_txd o mfp3 data transmitter output pin for uart1. can0_rxd i mfp4 can bus receiver input. sc0_clk o mfp5 smartcard clock pin. pwm1_ch5 i/o mfp6 pwm1 output/capture input. ebi_ad0 i/o mfp7 ebi address/data bus bit 0. int0 i mfp8 external interrupt0 input pin. 53 v ss a mfp0 ground pin for digital circuit. 54 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 55 av dd a mfp0 power supply for internal analog circuit. 56 v ref i mfp0 voltage reference input for adc. note: this pin needs to be connected with a 1uf capacitor. 57 pb.0 i/o mfp0 general purpose digital i/o pin. eadc_ch0 a mfp1 eadc analog input.
m4 tk jan . 06 , 201 6 page 37 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description spi0_mosi1 i/o mfp2 spi0 2nd mosi (master out, slave in) pin. uart2_rxd i mfp3 data receiver input pin for uart2. t2 i/o mfp4 timer2 event counter input / toggle output dac a mfp5 dac analog output ebi_nwrl o mfp7 ebi low byte write enable output pin. int1 i mfp8 external interrupt1 input pin. 58 pb.1 i/o mfp0 general purpose digital i/o pin. eadc_ch1 a mfp1 e adc analog input channel 1. spi0_miso1 i/o mfp2 spi0 2nd miso (master in, slave out) pin. uart2_txd o mfp3 data transmitter output pin for uart2. t3 i/o mfp4 timer3 event counter input / toggle output sc0_rst o mfp5 smartcard reset pin. pwm0_sync_out o mfp6 pwm 0 counter synchronous trigger output pin. ebi_nwrh o mfp7 ebi high byte write enable output pin 59 pb.2 i/o mfp0 general purpose digital i/o pin. eadc_ch2 a mfp1 e adc analog input channel 2. spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin uart1_rxd i mfp4 data receiver input pin for uart1. sc0_cd i mfp5 smartcard card detect pin. 60 pb.3 i/o mfp0 general purpose digital i/o pin. eadc_ch3 a mfp1 e adc analog input channel 3. spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. uart1_txd o mfp4 data transmitter output pin for uart1. 61 pb.4 i/o mfp0 general purpose digital i/o pin. eadc_ch4 a mfp1 e adc analog input channel 4. spi0_ss i/o mfp2 spi0 slave select pin. spi1_ss i/o mfp3 spi1 slave select pin uart1_ncts i mfp4 clear to send input pin for uart1. acmp0_n a mfp5 comparator0 negative input pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7. 62 pb.8 i/o mfp0 general purpose digital i/o pin. eadc_ch5 a mfp1 e adc analog input channel 5.
m4 tk jan . 06 , 201 6 page 38 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description uart1_nrts o mfp4 request to send output pin for uart1. pwm0_ch2 i/o mfp6 pwm0 output/capture input. 63 pb.11 i/o mfp0 general purpose digital i/o pin. eadc_ch8 a mfp1 e adc analog input channel 8 . tk0 a mfp4 touch key0 . 64 pb.12 i/o mfp0 general purpose digital i/o pin. eadc_ch9 a mfp1 e adc analog input channel 9. tk1 a mfp4 touch key1 .
m4 tk jan . 06 , 201 6 page 39 of 144 rev .1.00 m4tk series datashee t 4.3.3 m4tk can series(can+usb) lqfp100 pin description mfp* = multi - function pin. ( refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[3:0] = 0x0. pa.9 mfp5 means sys_gpa_mfph[7:4] = 0x5. pin no . pin name type mfp * description 1 pb.13 i/o mfp0 general purpose digital i/o pin. eadc_ch10 a mfp1 e adc analog input channel 10 . 2 pb.14 i/o mfp0 general purpose digital i/o pin. eadc_ch11 a mfp1 e adc analog input channel 11 . 3 pb.15 i/o mfp0 general purpose digital i/o pin. eadc_ch12 a mfp1 e adc analog input channel 12 . tk2 a mfp4 touch key2 . acmp0_p3 a mfp5 comparator0 positive input pin. ebi_ncs1 o mfp7 ebi chip select 1 enable output pin. 4 pb.5 i/o mfp0 general purpose digital i/o pin. eadc_ch13 a mfp1 e adc analog input channel 13 . spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. spi1_mosi i/o mfp3 spi1 mosi (master out, slave in) pin. tk3 a mfp4 touch key3 . acmp0_p2 a mfp5 comparator0 positive input pin. ebi_ad6 i/o mfp7 ebi address/data bus bit 6. 5 pb.6 i/o mfp0 general purpose digital i/o pin. eadc_ch14 a mfp1 e adc analog input channel 14 . spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin. tk4 a mfp4 touch key4 . acmp0_p1 a mfp5 comparator0 positive input pin. ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 6 pb.7 i/o mfp0 general purpose digital i/o pin. eadc_ch15 a mfp1 e adc analog input channel 15 . spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin tk5 a mfp4 touch key5 . acmp0_p0 a mfp5 comparator0 positive input pin. ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 7 nreset i mfp0 external reset input: active low, with an internal pull - up.
m4 tk jan . 06 , 201 6 page 40 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description set this pin low reset to initial state. 8 pd.0 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk o mfp2 i2s1 master clock output pin. uart0_rxd i mfp3 data receiver input pin for uart0. tk6 a mfp4 touch key6 . acmp1_n a mfp5 comparator1 negative input pin. int3 i mfp8 external interrupt3 input pin. 9 av ss p mfp0 ground pin for analog circuit. 10 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 11 v ss a mfp0 ground pin for digital circuit. 12 pc.8 i/o mfp0 general purpose digital i/o pin. tk7 a mfp4 touch key7 . 13 pd.8 i/o mfp0 general purpose digital i/o pin. tk8 a mfp4 touch key0 . ebi_ncs0 o mfp7 ebi chip select 0 enable output pin. 14 pd.9 i/o mfp0 general purpose digital i/o pin. tk9 a mfp4 touch key8 . acmp1_p3 a mfp5 comparator1 positive input pin. ebi_ale o mfp7 ebi address latch enable output pin. 15 pd.1 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp2 pwm 0 counter synchronous trigger input pin. uart0_txd o mfp3 data transmitter output pin for uart0. tk10 a mfp4 touch key10 . acmp1_p2 a mfp5 comparator1 positive input pin. t0 i/o mfp6 timer0event counter input / toggle output ebi_nrd o mfp7 ebi read enable output pin. 16 pd.2 i/o mfp0 general purpose digital i/o pin. stadc i mfp1 adc external trigger input. t0_ext i mfp3 timer0 external capture input . tk11 a mfp4 touch key11 . acmp1_p1 a mfp5 comparator1 positive input pin. pwm0_brake0 i mfp6 pwm0 break input 0 ebi_nwr o mfp7 ebi write enable output pin. int0 i mfp8 external interrupt0 input pin.
m4 tk jan . 06 , 201 6 page 41 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 17 pd.3 i/o mfp0 general purpose digital i/o pin. t2 i/o mfp1 timer2 event counter input / toggle output t1_ext i mfp3 timer1 external capture input tk12 a mfp4 touch key12 . acmp1_p0 a mfp5 comparator1 positive input pin. pwm0_brake1 i mfp6 pwm0 break input 1 ebi_mclk o mfp7 ebi external clock output pin int1 i mfp8 external interrupt1 input pin. 18 pd.4 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp2 spi1 serial clock pin i2c0_sda i/o mfp3 i2c0 data input/output pin. tk13 a mfp4 touch key13 . pwm0_brake0 i mfp5 pwm0 break input 0 t0 i/o mfp6 timer0event counter input / toggle output 19 pd.5 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out spi1_miso i/o mfp2 spi1 miso (master in, slave out) pin. i2c0_scl i/o mfp3 i2c0 clock pin. tk14 a mfp4 touch key14 . pwm0_brake1 i mfp5 pwm0 break input 1 t1 i/o mfp6 timer1 event counter input / toggle output 20 pe.3 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp2 spi1 mosi (master out, slave in) pin. tk15 a mfp4 touch key15 . pwm0_ch3 i/o mfp6 pwm0 output/capture input. 21 pd.6 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out spi1_ss i/o mfp2 spi1 slave select pin uart0_rxd i mfp3 data receiver input pin for uart0. tk16 a mfp4 touch key16 . acmp0_o o mfp5 comparator0 output . pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_nwr o mfp7 ebi write enable output pin. 22 v bat a mfp0 power supply by batteries for rtc and pf.0~pf.2 .
m4 tk jan . 06 , 201 6 page 42 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 23 pf.0 i/o mfp0 general purpose digital i/o pin. x32_out o mfp1 external 32.768 khz (low speed) crystal output pin. int5 i mfp8 external interrupt5 input pin. 24 pf.1 i/o mfp0 general purpose digital i/o pin. x32_in i mfp1 external 32.768 khz (low speed) crystal input pin. 25 pf.2 i/o mfp0 general purpose digital i/o pin. tamper i/o mfp1 tamper detector loop pin 26 pd.10 i/o mfp0 general purpose digital i/o pin. t2 i/o mfp4 timer2 event counter input / toggle output 27 pd.11 i/o mfp0 general purpose digital i/o pin. t3 i/o mfp4 timer3 event counter input / toggle output . 28 pd.12 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. uart3_txd o mfp3 data transmitter output pin for uart3. pwm1_ch0 i/o mfp6 pwm1 output/capture input. ebi_adr16 o mfp7 ebi address bus bit 16. 29 pd.13 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin. uart3_rxd i mfp3 data receiver input pin for uart3. pwm1_ch1 i/o mfp6 pwm1 output/capture input. ebi_adr17 o mfp7 ebi address bus bit 17. 30 pd.14 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. uart3_ncts i mfp3 clear to send input pin for uart3. pwm1_ch2 i/o mfp6 pwm1 output/capture input. ebi_adr18 o mfp7 ebi address bus bit 18. 31 pd.15 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. uart3_nrts o mfp3 request to send output pin for uart3. pwm1_ch3 i/o mfp6 pwm1 output/capture input. ebi_adr19 o mfp7 ebi address bus bit 19. 32 pd.7 i/o mfp0 general purpose digital i/o pin. pwm0_sync_in i mfp3 pwm 0 counter synchronous trigger input pin. t1 i/o mfp4 timer1 event counter input / toggle output
m4 tk jan . 06 , 201 6 page 43 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description acmp0_o o mfp5 comparator0 output. pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_nrd o mfp7 ebi read enable output pin. 33 pf.3 i/o mfp0 general purpose digital i/o pin. xt1_out o mfp1 external 4~20 mhz (high speed) crystal output pin. i2c1_scl i/o mfp3 i2c1 clock pin. 34 pf.4 i/o mfp0 general purpose digital i/o pin. xt1_in i mfp1 external 4~20 mhz (high speed) crystal input pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. 35 v ss a mfp0 ground pin for digital circuit. 36 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 37 ldo_cap a mfp0 ldo output pin. note: this pin needs to be connected with a 1uf capacitor. 38 pc.9 i/o mfp0 general purpose digital i/o pin. spi2_i2smclk o mfp2 i2s2 master clock output pin. pwm1_ch0 i/o mfp6 pwm1 output/capture input. 39 pc.10 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin. pwm1_ch1 i/o mfp6 pwm1 output/capture input. 40 pc.11 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. pwm1_ch2 i/o mfp6 pwm1 output/capture input. 41 pc.12 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. pwm1_ch3 i/o mfp6 pwm1 output/capture input. 42 pc.13 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. pwm1_ch4 i/o mfp6 pwm1 output/capture input. 43 pc.14 i/o mfp0 general purpose digital i/o pin. pwm1_ch5 i/o mfp6 pwm1 output/capture input. 44 pc.0 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. uart2_ncts i mfp3 clear to send input pin for uart2. can0_txd i mfp4 can bus transmitter input.
m4 tk jan . 06 , 201 6 page 44 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description pwm0_ch0 i/o mfp6 pwm0 output/capture input. ebi_ad8 i/o mfp7 ebi address/data bus bit 8. int2 i mfp8 external interrupt2 input pin. 45 pc.1 i/o mfp0 general purpose digital i/o pin. clko o mfp1 clock out stdac i mfp2 dac external trigger input. uart2_nrts o mfp3 request to send output pin for uart2. can0_rxd i mfp4 can bus receiver input. pwm0_ch1 i/o mfp6 pwm0 output/capture input. ebi_ad9 i/o mfp7 ebi address/data bus bit 9. 46 pc.2 i/o mfp0 general purpose digital i/o pin. spi2_ss i mfp2 spi2 slave select pin. uart2_txd o mfp3 data transmitter output pin for uart2. acmp1_o o mfp5 comparator1 output . pwm0_ch2 i/o mfp6 pwm0 output/capture input. ebi_ad10 i/o mfp7 ebi address/data bus bit 10. 47 pc.3 i/o mfp0 general purpose digital i/o pin. spi2_mosi i/o mfp2 spi2 mosi (master out, slave in) pin. uart2_rxd i mfp3 data receiver input pin for uart2. usb_ vbus _st i mfp4 usb external vbus regulator status pin. pwm0_ch3 i/o mfp6 pwm0 output/capture input. ebi_ad11 i/o mfp7 ebi address/data bus bit 11. 48 pc.4 i/o mfp0 general purpose digital i/o pin. spi2_miso i/o mfp2 spi2 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i2c1 clock pin. usb_ vbus _en o mfp4 usb external vbus regulator enable pin. pwm0_ch4 i/o mfp6 pwm0 output/capture input. ebi_ad12 i/o mfp7 ebi address/data bus bit 12. 49 pe.0 i/o mfp0 general purpose digital i/o pin. spi2_clk i/o mfp2 spi2 serial clock pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. t2_ext i mfp4 timer2 external capture input sc0_cd i mfp5 smartcard card detect pin. pwm0_ch0 i/o mfp6 pwm0 output/capture input.
m4 tk jan . 06 , 201 6 page 45 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description ebi_ncs1 o mfp7 ebi chip select 1 enable output pin. int4 i mfp8 external interrupt4 input pin. 50 pc.5 i/o mfp0 general purpose digital i/o pin. spi2_i2smclk o mfp2 i2s2 master clock output pin. pwm0_ch5 i/o mfp6 pwm0 output/capture input. ebi_ad13 i/o mfp7 ebi address/data bus bit 13. 51 pc.6 i/o mfp0 general purpose digital i/o pin. i2c1_smbal o mfp3 i2c1 smbus smbalter# pin acmp1_o o mfp5 comparator1 output . pwm1_ch0 i/o mfp6 pwm1 output/capture input. ebi_ad14 i/o mfp7 ebi address/data bus bit 14. 52 pc.7 i/o mfp0 general purpose digital i/o pin. i2c1_smbsus o mfp3 i2c1 smbus smbsus# pin (pmbus control pin) pwm1_ch1 i/o mfp6 pwm1 output/capture input. ebi_ad15 i/o mfp7 ebi address/data bus bit 15. 53 pe.4 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp3 i2c1 clock pin. sc0_pwr o mfp5 smartcard power pin. pwm1_brake0 i mfp6 pwm1 break input 0 ebi_ncs0 o mfp7 ebi chip select 0 enable output pin. int0 i mfp8 external interrupt0 input pin. 54 pe.5 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp3 i2c1 data input/output pin. sc0_rst o mfp5 smartcard reset pin. pwm1_brake1 i mfp6 pwm1 break input 1 ebi_ale o mfp7 ebi address latch enable output pin. int1 i mfp8 external interrupt1 input pin. 55 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin 56 pf.6 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin 57 pa.8 i/o mfp0 general purpose digital i/o pin. uart3_txd o mfp3 data transmitter output pin for uart3. 58 pa.9 i/o mfp0 general purpose digital i/o pin.
m4 tk jan . 06 , 201 6 page 46 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description uart3_rxd i mfp3 data receiver input pin for uart3. 59 pa.7 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp2 spi1 serial clock pin t0_ext i mfp3 timer0 external capture input . ebi_ad7 i/o mfp7 ebi address/data bus bit 7. 60 pa.6 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp2 spi1 miso (master in, slave out) pin. t1_ext i mfp3 timer1 external capture input ebi_ad6 i/o mfp7 ebi address/data bus bit 6. 61 pa.5 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp2 spi1 mosi (master out, slave in) pin. t2_ext i mfp3 timer2 external capture input ebi_ad5 i/o mfp7 ebi address/data bus bit 5. 62 pa.4 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp2 spi1 slave select pin ebi_ad4 i/o mfp7 ebi address/data bus bit 4. 63 v ss a mfp0 ground pin for digital circuit. 64 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 65 pe.1 i/o mfp0 general purpose digital i/o pin. t3_ext i mfp3 timer3 external capture input sc0_cd i mfp5 smartcard card detect pin. pwm0_ch1 i/o mfp6 pwm0 output/capture input. 66 pe.8 i/o mfp0 general purpose digital i/o pin. uart1_txd o mfp1 data transmitter output pin for uart1. spi0_miso1 i/o mfp2 spi0 2nd miso (master in, slave out) pin. i2c1_scl i/o mfp4 i2c1 clock pin. sc0_pwr o mfp5 smartcard power pin. 67 pe.9 i/o mfp0 general purpose digital i/o pin. uart1_rxd i mfp1 data receiver input pin for uart1. spi0_mosi1 i/o mfp2 spi0 2nd mosi (master out, slave in) pin. i2c1_sda i/o mfp4 i2c1 data input/output pin. sc0_rst o mfp5 smartcard reset pin. 68 pe.10 i/o mfp0 general purpose digital i/o pin. spi1_miso i/o mfp1 spi1 miso (master in, slave out) pin.
m4 tk jan . 06 , 201 6 page 47 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. uart1_ncts i mfp3 clear to send input pin for uart1. i2c0_smbal o mfp4 i2c0 smbus smbalter# pin sc0_dat i/o mfp5 smartcard data pin. 69 pe.11 i/o mfp0 general purpose digital i/o pin. spi1_mosi i/o mfp1 spi1 mosi (master out, slave in) pin. spi0_mosi0 i/o mfp2 spi0 1st mosi (master out, slave in) pin. uart1_nrts o mfp3 request to send output pin for uart1. i2c0_smbsus o mfp4 i2c0 smbus smbsus# pin (pmbus control pin) sc0_clk o mfp5 smartcard clock pin. 70 pe.12 i/o mfp0 general purpose digital i/o pin. spi1_ss i/o mfp1 spi1 slave select pin spi0_ss i/o mfp2 spi0 slave select pin. uart1_txd o mfp3 data transmitter output pin for uart1. i2c0_scl i/o mfp4 i2c0 clock pin. 71 pe.13 i/o mfp0 general purpose digital i/o pin. spi1_clk i/o mfp1 spi1 serial clock pin spi0_clk i/o mfp2 spi0 serial clock pin. uart1_rxd i mfp3 data receiver input pin for uart1. i2c0_sda i/o mfp4 i2c0 data input/output pin. 72 v dd io a mfp0 power supply for pe.8~pe.13 . 73 usb_vbus a mfp0 power supply from usb* host or hub. 74 usb_d - i mfp0 usb differential signal d - . 75 usb_d+ i mfp0 usb differential signal d+. usb_id i mfp0 usb identification. 77 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. note: this pin needs to be connected with a 1uf capacitor. 78 pe.2 i/o mfp0 general purpose digital i/o pin. pwm1_ch1 i/o mfp6 pwm1 output/capture input. 79 pa.3 i/o mfp0 general purpose digital i/o pin. usb_ vbus _st i mfp1 usb external vbus regulator status pin. uart0_rxd i mfp2 data receiver input pin for uart0. uart0_nrts o mfp3 request to send output pin for uart0. i2c0_scl i/o mfp4 i2c0 clock pin.
m4 tk jan . 06 , 201 6 page 48 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description sc0_pwr o mfp5 smartcard power pin. pwm1_ch2 i/o mfp6 pwm1 output/capture input. ebi_ad3 i/o mfp7 ebi address/data bus bit 3. 80 pa.2 i/o mfp0 general purpose digital i/o pin. usb_v bus _en o mfp1 usb external vbus regulator enable pin. uart0_txd o mfp2 data transmitter output pin for uart0. uart0_ncts i mfp3 clear to send input pin for uart0. i2c0_sda i/o mfp4 i2c0 data input/output pin. sc0_rst o mfp5 smartcard reset pin. pwm1_ch3 i/o mfp6 pwm1 output/capture input. ebi_ad2 i/o mfp7 ebi address/data bus bit 2. 81 pa.1 i/o mfp0 general purpose digital i/o pin. uart1_nrts o mfp1 request to send output pin for uart1. uart1_rxd i mfp3 data receiver input pin for uart1. can0_txd i mfp4 can bus transmitter input. sc0_dat i/o mfp5 smartcard data pin. pwm1_ch4 i/o mfp6 pwm1 output/capture input. ebi_ad1 i/o mfp7 ebi address/data bus bit 1. 82 pa.0 i/o mfp0 general purpose digital i/o pin. uart1_ncts i mfp1 clear to send input pin for uart1. uart1_txd o mfp3 data transmitter output pin for uart1. can0_rxd i mfp4 can bus receiver input. sc0_clk o mfp5 smartcard clock pin. pwm1_ch5 i/o mfp6 pwm1 output/capture input. ebi_ad0 i/o mfp7 ebi address/data bus bit 0. int0 i mfp8 external interrupt0 input pin. 83 pa.12 i/o mfp0 general purpose digital i/o pin. spi1_i2smclk o mfp2 i2s1 master clock output pin. can0_txd i mfp4 can bus transmitter input. 84 pa.13 i/o mfp0 general purpose digital i/o pin. can0_rxd i mfp4 can bus receiver input. 85 pa.14 i/o mfp0 general purpose digital i/o pin. uart2_ncts i mfp3 clear to send input pin for uart2. i2c0_smbal o mfp4 i2c0 smbus smbalter# pin
m4 tk jan . 06 , 201 6 page 49 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description 86 pa.15 i/o mfp0 general purpose digital i/o pin. uart2_nrts o mfp3 request to send output pin for uart2. i2c0_smbsus o mfp4 i2c0 smbus smbsus# pin (pmbus control pin) 87 v ss a mfp0 ground pin for digital circuit. 88 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 89 av dd a mfp0 power supply for internal analog circuit. 90 v ref i mfp0 voltage reference input for adc. note: this pin needs to be connected with a 1uf capacitor. 91 pb.0 i/o mfp0 general purpose digital i/o pin. eadc_ch0 a mfp1 eadc analog input. spi0_mosi1 i/o mfp2 spi0 2nd mosi (master out, slave in) pin. uart2_rxd i mfp3 data receiver input pin for uart2. t2 i/o mfp4 timer2 event counter input / toggle output dac a mfp5 dac analog output ebi_nwrl o mfp7 ebi low byte write enable output pin. int1 i mfp8 external interrupt1 input pin. 92 pb.1 i/o mfp0 general purpose digital i/o pin. eadc_ch1 a mfp1 e adc analog input channel 1 . spi0_miso1 i/o mfp2 spi0 2nd miso (master in, slave out) pin. uart2_txd o mfp3 data transmitter output pin for uart2. t3 i/o mfp4 timer3 event counter input / toggle output sc0_rst o mfp5 smartcard reset pin. pwm0_sync_out o mfp6 pwm 0 counter synchronous trigger output pin. ebi_nwrh o mfp7 ebi high byte write enable output pin 93 pb.2 i/o mfp0 general purpose digital i/o pin. eadc_ch2 a mfp1 e adc analog input channel 2 . spi0_clk i/o mfp2 spi0 serial clock pin. spi1_clk i/o mfp3 spi1 serial clock pin uart1_rxd i mfp4 data receiver input pin for uart1. sc0_cd i mfp5 smartcard card detect pin. 94 pb.3 i/o mfp0 general purpose digital i/o pin. eadc_ch3 a mfp1 e adc analog input channel 3 . spi0_miso0 i/o mfp2 spi0 1st miso (master in, slave out) pin. spi1_miso i/o mfp3 spi1 miso (master in, slave out) pin.
m4 tk jan . 06 , 201 6 page 50 of 144 rev .1.00 m4tk series datashee t pin no . pin name type mfp * description uart1_txd o mfp4 data transmitter output pin for uart1. 95 pb.4 i/o mfp0 general purpose digital i/o pin. eadc_ch4 a mfp1 e adc analog input channel 4 . spi0_ss i/o mfp2 spi0 slave select pin. spi1_ss i/o mfp3 spi1 slave select pin uart1_ncts i mfp4 clear to send input pin for uart1. acmp0_n a mfp5 comparator0 negative input pin. ebi_ad7 i/o mfp7 ebi address/data bus bit 7. 96 pb.8 i/o mfp0 general purpose digital i/o pin. eadc_ch5 a mfp1 e adc analog input channel 5 . uart1_nrts o mfp4 request to send output pin for uart1. pwm0_ch2 i/o mfp6 pwm0 output/capture input. 97 pb.9 i/o mfp0 general purpose digital i/o pin. eadc_ch6 a mfp1 e adc analog input channel 6 . 98 pb.10 i/o mfp0 general purpose digital i/o pin. eadc_ch7 a mfp1 e adc analog input channel 7 . 99 pb.11 i/o mfp0 general purpose digital i/o pin. eadc_ch8 a mfp1 e adc analog input channel 8 . tk0 a mfp4 touch key0 . 100 pb.12 i/o mfp0 general purpose digital i/o pin. eadc_ch9 a mfp1 e adc analog input channel 9 . tk1 a mfp4 touch key1 .
m4 tk jan . 06 , 201 6 page 51 of 144 rev .1.00 m4tk series datashee t 4.3.4 gpio multi - function pin summary mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.0 mfp0 means sys_gpa_mfpl[3:0]=0x0. pa.9 mfp5 means sys_gpa_mfph[7:4]=0x5. group pin name mfp * type description acmp0 acmp0_n mfp5 a comparator0 negative input pin. acmp0_o mfp5 o comparator0 output. acmp0_o mfp5 o comparator0 output. acmp0_p0 mfp5 a comparator0 positive input pin. acmp0_p1 mfp5 a comparator0 positive input pin. acmp0_p2 mfp5 a comparator0 positive input pin. acmp0_p3 mfp5 a comparator0 positive input pin. acmp1 acmp1_n mfp5 a comparator1 negative input pin. acmp1_o mfp5 o comparator1 output . acmp1_o mfp5 o comparator1 output . acmp1_p0 mfp5 a comparator1 positive input pin. acmp1_p1 mfp5 a comparator1 positive input pin. acmp1_p2 mfp5 a comparator1 positive input pin. acmp1_p3 mfp5 a comparator1 positive input pin. e adc e adc_ch0 mfp1 a adc0 analog input. e adc_ch1 mfp1 a adc1 analog input. e adc_ch2 mfp1 a adc2 analog input. e adc_ch3 mfp1 a adc3 analog input. e adc_ch4 mfp1 a adc4 analog input. e adc_ch5 mfp1 a adc5 analog input. e adc_ch6 mfp1 a adc6 analog input. e adc_ch7 mfp1 a adc7 analog input. e adc_ch8 mfp1 a adc8 analog input. e adc_ch9 mfp1 a adc9 analog input. e adc_ch10 mfp1 a adc10 analog input. e adc_ch11 mfp1 a adc11 analog input. e adc_ch12 mfp1 a adc12 analog input. e adc_ch13 mfp1 a adc13 analog input. e adc_ch14 mfp1 a adc14 analog input. e adc_ch15 mfp1 a adc15 analog input. stadc mfp1 i adc external trigger input.
m4 tk jan . 06 , 201 6 page 52 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description can0 can0_rxd mfp4 i can bus receiver input. can0_rxd mfp4 i can bus receiver input. can0_rxd mfp4 i can bus receiver input. can0_txd mfp4 i can bus transmitter input. can0_txd mfp4 i can bus transmitter input. can0_txd mfp4 i can bus transmitter input. clko clko mfp1 o clock out clko mfp1 o clock out clko mfp1 o clock out dac dac mfp5 a dac analog output stdac mfp2 i dac external trigger input. ebi ebi_ad0 mfp7 i/o ebi address/data bus bit 0. ebi_ad1 mfp7 i/o ebi address/data bus bit 1. ebi_ad2 mfp7 i/o ebi address/data bus bit 2. ebi_ad3 mfp7 i/o ebi address/data bus bit 3. ebi_ad4 mfp7 i/o ebi address/data bus bit 4. ebi_ad4 mfp7 i/o ebi address/data bus bit 4. ebi_ad5 mfp7 i/o ebi address/data bus bit 5. ebi_ad5 mfp7 i/o ebi address/data bus bit 5. ebi_ad6 mfp7 i/o ebi address/data bus bit 6. ebi_ad6 mfp7 i/o ebi address/data bus bit 6. ebi_ad7 mfp7 i/o ebi address/data bus bit 7. ebi_ad7 mfp7 i/o ebi address/data bus bit 7. ebi_ad8 mfp7 i/o ebi address/data bus bit 8. ebi_ad9 mfp7 i/o ebi address/data bus bit 9. ebi_ad10 mfp7 i/o ebi address/data bus bit 10. ebi_ad11 mfp7 i/o ebi address/data bus bit 11. ebi_ad12 mfp7 i/o ebi address/data bus bit 12. ebi_ad13 mfp7 i/o ebi address/data bus bit 13. ebi_ad14 mfp7 i/o ebi address/data bus bit 14. ebi_ad15 mfp7 i/o ebi address/data bus bit 15. ebi_adr16 mfp7 o ebi address bus bit 16. ebi_adr17 mfp7 o ebi address bus bit 17. ebi_adr18 mfp7 o ebi address bus bit 18.
m4 tk jan . 06 , 201 6 page 53 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description ebi_adr19 mfp7 o ebi address bus bit 19. ebi_ale mfp7 o ebi address latch enable output pin. ebi_ale mfp7 o ebi address latch enable output pin. ebi_mclk mfp7 o ebi external clock output pin ebi_ncs0 mfp7 o ebi chip select 0 enable output pin. ebi_ncs0 mfp7 o ebi chip select 0 enable output pin. ebi_ncs1 mfp7 o ebi chip select 1 enable output pin. ebi_ncs1 mfp7 o ebi chip select 1 enable output pin. ebi_nrd mfp7 o ebi read enable output pin. ebi_nrd mfp7 o ebi read enable output pin. ebi_nwr mfp7 o ebi write enable output pin. ebi_nwr mfp7 o ebi write enable output pin. ebi_nwrh mfp7 o ebi high byte write enable output pin ebi_nwrl mfp7 o ebi low byte write enable output pin. i2c0 i2c0_scl mfp3 i/o i2c0 clock pin. i2c0_scl mfp4 i/o i2c0 clock pin. i2c0_scl mfp4 i/o i2c0 clock pin. i2c0_sda mfp3 i/o i2c0 data input/output pin. i2c0_sda mfp4 i/o i2c0 data input/output pin. i2c0_sda mfp4 i/o i2c0 data input/output pin. i2c0_smbal mfp4 o i2c0 smbus smbalter# pin i2c0_smbal mfp4 o i2c0 smbus smbalter# pin i2c0_smbsus mfp4 o i2c0 smbus smbsus# pin (pmbus control pin) i2c0_smbsus mfp4 o i2c0 smbus smbsus# pin (pmbus control pin) i2c1 i2c1_scl mfp3 i/o i2c1 clock pin. i2c1_scl mfp3 i/o i2c1 clock pin. i2c1_scl mfp3 i/o i2c1 clock pin. i2c1_scl mfp4 i/o i2c1 clock pin. i2c1_sda mfp3 i/o i2c1 data input/output pin. i2c1_sda mfp3 i/o i2c1 data input/output pin. i2c1_sda mfp3 i/o i2c1 data input/output pin. i2c1_sda mfp4 i/o i2c1 data input/output pin. i2c1_smbal mfp3 o i2c1 smbus smbalter# pin i2c1_smbsus mfp3 o i2c1 smbus smbsus# pin (pmbus control pin)
m4 tk jan . 06 , 201 6 page 54 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description i2s1 spi1_i2smclk mfp2 o i2s1 master clock output pin. spi1_i2smclk mfp2 o i2s1 master clock output pin. i2s2 spi2_i2smclk mfp2 o i2s2 master clock output pin. spi2_i2smclk mfp2 o i2s2 master clock output pin. ice ice_clk mfp1 i serial wired debugger clock pin ice_dat mfp1 i/o serial wired debugger data pin int0 int0 mfp8 i external interrupt0 input pin. int0 mfp8 i external interrupt0 input pin. int0 mfp8 i external interrupt0 input pin. int1 int1 mfp8 i external interrupt1 input pin. int1 mfp8 i external interrupt1 input pin. int1 mfp8 i external interrupt1 input pin. int2 int2 mfp8 i external interrupt2 input pin. int3 int3 mfp8 i external interrupt3 input pin. int4 int4 mfp8 i external interrupt4 input pin. int5 int5 mfp8 i external interrupt5 input pin. pwm0 pwm0_brake0 mfp6 i pwm0 break input 0 pwm0_brake0 mfp5 i pwm0 break input 0 pwm0_brake1 mfp6 i pwm0 break input 1 pwm0_brake1 mfp5 i pwm0 break input 1 pwm0_ch0 mfp6 i/o pwm0 output/capture input. pwm0_ch0 mfp6 i/o pwm0 output/capture input. pwm0_ch1 mfp6 i/o pwm0 output/capture input. pwm0_ch1 mfp6 i/o pwm0 output/capture input. pwm0_ch2 mfp6 i/o pwm0 output/capture input. pwm0_ch2 mfp6 i/o pwm0 output/capture input. pwm0_ch3 mfp6 i/o pwm0 output/capture input. pwm0_ch3 mfp6 i/o pwm0 output/capture input. pwm0_ch4 mfp6 i/o pwm0 output/capture input. pwm0_ch5 mfp6 i/o pwm0 output/capture input. pwm0_ch5 mfp6 i/o pwm0 output/capture input. pwm0_ch5 mfp6 i/o pwm0 output/capture input. pwm0_sync_in mfp2 i pwm 0 counter synchronous trigger input pin. pwm0_sync_in mfp3 i pwm 0 counter synchronous trigger input pin.
m4 tk jan . 06 , 201 6 page 55 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description pwm0_sync_out mfp6 o pwm 0 counter synchronous trigger output pin. pwm1 pwm1_brake0 mfp6 i pwm1 break input 0 pwm1_brake1 mfp6 i pwm1 break input 1 pwm1_ch0 mfp6 i/o pwm1 output/capture input. pwm1_ch0 mfp6 i/o pwm1 output/capture input. pwm1_ch0 mfp6 i/o pwm1 output/capture input. pwm1_ch0 mfp6 i/o pwm1 output/capture input. pwm1_ch1 mfp6 i/o pwm1 output/capture input. pwm1_ch1 mfp6 i/o pwm1 output/capture input. pwm1_ch1 mfp6 i/o pwm1 output/capture input. pwm1_ch1 mfp6 i/o pwm1 output/capture input. pwm1_ch2 mfp6 i/o pwm1 output/capture input. pwm1_ch2 mfp6 i/o pwm1 output/capture input. pwm1_ch2 mfp6 i/o pwm1 output/capture input. pwm1_ch3 mfp6 i/o pwm1 output/capture input. pwm1_ch3 mfp6 i/o pwm1 output/capture input. pwm1_ch3 mfp6 i/o pwm1 output/capture input. pwm1_ch4 mfp6 i/o pwm1 output/capture input. pwm1_ch4 mfp6 i/o pwm1 output/capture input. pwm1_ch5 mfp6 i/o pwm1 output/capture input. pwm1_ch5 mfp6 i/o pwm1 output/capture input. sc0 sc0_cd mfp5 i smartcard card detect pin. sc0_cd mfp5 i smartcard card detect pin. sc0_cd mfp5 i smartcard card detect pin. sc0_clk mfp5 o smartcard clock pin. sc0_clk mfp5 o smartcard clock pin. sc0_dat mfp5 i/o smartcard data pin. sc0_dat mfp5 i/o smartcard data pin. sc0_pwr mfp5 o smartcard power pin. sc0_pwr mfp5 o smartcard power pin. sc0_pwr mfp5 o smartcard power pin. sc0_rst mfp5 o smartcard reset pin. sc0_rst mfp5 o smartcard reset pin. sc0_rst mfp5 o smartcard reset pin.
m4 tk jan . 06 , 201 6 page 56 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description sc0_rst mfp5 o smartcard reset pin. spi0 spi0_clk mfp2 i/o spi0 serial clock pin. spi0_clk mfp2 i/o spi0 serial clock pin. spi0_clk mfp2 i/o spi0 serial clock pin. spi0_miso0 mfp2 i/o spi0 1st miso (master in, slave out) pin. spi0_miso0 mfp2 i/o spi0 1st miso (master in, slave out) pin. spi0_miso0 mfp2 i/o spi0 1st miso (master in, slave out) pin. spi0_miso1 mfp2 i/o spi0 2nd miso (master in, slave out) pin. spi0_miso1 mfp2 i/o spi0 2nd miso (master in, slave out) pin. spi0_mosi0 mfp2 i/o spi0 1st mosi (master out, slave in) pin. spi0_mosi0 mfp2 i/o spi0 1st mosi (master out, slave in) pin. spi0_mosi1 mfp2 i/o spi0 2nd mosi (master out, slave in) pin. spi0_mosi1 mfp2 i/o spi0 2nd mosi (master out, slave in) pin. spi0_ss mfp2 i/o spi0 slave select pin. spi0_ss mfp2 i/o spi0 slave select pin. spi1 spi1_clk mfp3 i/o spi1 serial clock pin spi1_clk mfp2 i/o spi1 serial clock pin spi1_clk mfp2 i/o spi1 serial clock pin spi1_clk mfp1 i/o spi1 serial clock pin spi1_clk mfp3 i/o spi1 serial clock pin spi1_miso mfp3 i/o spi1 miso (master in, slave out) pin. spi1_miso mfp2 i/o spi1 miso (master in, slave out) pin. spi1_miso mfp2 i/o spi1 miso (master in, slave out) pin. spi1_miso mfp1 i/o spi1 miso (master in, slave out) pin. spi1_miso mfp3 i/o spi1 miso (master in, slave out) pin. spi1_mosi mfp3 i/o spi1 mosi (master out, slave in) pin. spi1_mosi mfp2 i/o spi1 mosi (master out, slave in) pin. spi1_mosi mfp2 i/o spi1 mosi (master out, slave in) pin. spi1_mosi mfp1 i/o spi1 mosi (master out, slave in) pin. spi1_ss mfp2 i/o spi1 slave select pin spi1_ss mfp2 i/o spi1 slave select pin spi1_ss mfp1 i/o spi1 slave select pin spi1_ss mfp3 i/o spi1 slave select pin spi2 spi2_clk mfp2 i/o spi2 serial clock pin.
m4 tk jan . 06 , 201 6 page 57 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description spi2_clk mfp2 i/o spi2 serial clock pin. spi2_clk mfp2 i/o spi2 serial clock pin. spi2_clk mfp2 i/o spi2 serial clock pin. spi2_miso mfp2 i/o spi2 miso (master in, slave out) pin. spi2_miso mfp2 i/o spi2 miso (master in, slave out) pin. spi2_miso mfp2 i/o spi2 miso (master in, slave out) pin. spi2_mosi mfp2 i/o spi2 mosi (master out, slave in) pin. spi2_mosi mfp2 i/o spi2 mosi (master out, slave in) pin. spi2_mosi mfp2 i/o spi2 mosi (master out, slave in) pin. spi2_ss mfp2 i spi2 slave select pin. spi2_ss mfp2 i spi2 slave select pin. spi2_ss mfp2 i spi2 slave select pin. tamper tamper mfp1 i/o tamper detector loop pin tk tk0 mfp4 a touch key0 tk1 mfp4 a touch key1 tk2 mfp4 a touch key2 tk3 mfp4 a touch key3 tk4 mfp4 a touch key4 tk5 mfp4 a touch key5 tk6 mfp4 a touch key6 tk7 mfp4 a touch key7 tk8 mfp4 a touch key0 tk9 mfp4 a touch key8 tk10 mfp4 a touch key10 tk11 mfp4 a touch key11 tk12 mfp4 a touch key12 tk13 mfp4 a touch key13 tk14 mfp4 a touch key14 tk15 mfp4 a touch key15 tk16 mfp4 a touch key16 tm r 0 t0 mfp6 i/o timer0event counter input / toggle output t0 mfp6 i/o timer0event counter input / toggle output t0_ext mfp3 i timer0 external capture input t0_ext mfp3 i timer0 external capture input
m4 tk jan . 06 , 201 6 page 58 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description tm r 1 t1 mfp6 i/o timer1 event counter input / toggle output t1 mfp4 i/o timer1 event counter input / toggle output t1_ext mfp3 i timer1 external capture input t1_ext mfp3 i timer1 external capture input tm r 2 t2 mfp1 i/o timer2 event counter input / toggle output t2 mfp4 i/o timer2 event counter input / toggle output t2 mfp4 i/o timer2 event counter input / toggle output t2_ext mfp4 i timer2 external capture input t2_ext mfp3 i timer2 external capture input tm r 3 t3 mfp4 i/o timer3 event counter input / toggle output t3 mfp4 i/o timer3 event counter input / toggle output t3_ext mfp3 i timer3 external capture input t3_ext mfp3 i timer3 external capture input uart0 uart0_rxd mfp3 i data receiver input pin for uart0. uart0_rxd mfp3 i data receiver input pin for uart0. uart0_rxd mfp2 i data receiver input pin for uart0. uart0_txd mfp3 o data transmitter output pin for uart0. uart0_txd mfp2 o data transmitter output pin for uart0. uart0_ncts mfp3 i clear to send input pin for uart0. uart0_nrts mfp3 o request to send output pin for uart0. uart1 uart1_rxd mfp1 i data receiver input pin for uart1. uart1_rxd mfp3 i data receiver input pin for uart1. uart1_rxd mfp3 i data receiver input pin for uart1. uart1_rxd mfp4 i data receiver input pin for uart1. uart1_txd mfp1 o data transmitter output pin for uart1. uart1_txd mfp3 o data transmitter output pin for uart1. uart1_txd mfp3 o data transmitter output pin for uart1. uart1_txd mfp4 o data transmitter output pin for uart1. uart1_ncts mfp3 i clear to send input pin for uart1. uart1_ncts mfp1 i clear to send input pin for uart1. uart1_ncts mfp4 i clear to send input pin for uart1. uart1_nrts mfp3 o request to send output pin for uart1. uart1_nrts mfp1 o request to send output pin for uart1. uart1_nrts mfp4 o request to send output pin for uart1.
m4 tk jan . 06 , 201 6 page 59 of 144 rev .1.00 m4tk series datashee t group pin name mfp * type description uart2 uart2_rxd mfp3 i data receiver input pin for uart2. uart2_rxd mfp3 i data receiver input pin for uart2. uart2_txd mfp3 o data transmitter output pin for uart2. uart2_txd mfp3 o data transmitter output pin for uart2. uart2_ncts mfp3 i clear to send input pin for uart2. uart2_ncts mfp3 i clear to send input pin for uart2. uart2_nrts mfp3 o request to send output pin for uart2. uart2_nrts mfp3 o request to send output pin for uart2. uart3 uart3_rxd mfp3 i data receiver input pin for uart3. uart3_rxd mfp3 i data receiver input pin for uart3. uart3_txd mfp3 o data transmitter output pin for uart3. uart3_txd mfp3 o data transmitter output pin for uart3. uart3_ncts mfp3 i clear to send input pin for uart3. uart3_ncts mfp3 i clear to send input pin for uart3. uart3_nrts mfp3 o request to send output pin for uart3. uart3_nrts mfp3 o request to send output pin for uart3. usb usb_v bus _en mfp4 o usb external vbus regulator enable pin. usb_v bus _en mfp1 o usb external vbus regulator enable pin. usb_v bus _st mfp4 i usb external vbus regulator status pin. usb_v bus _st mfp1 i usb external vbus regulator status pin. lxt x32_in mfp1 i external 32.768 khz (low speed) crystal input pin. x32_out mfp1 o external 32.768 khz (low speed) crystal output pin. hxt xt1_in mfp1 i external 4~20 mhz (high speed) crystal input pin. xt1_out mfp1 o external 4~20 mhz (high speed) crystal output pin. table 4 - 1 m4tk gpio multi - function table
m4 tk jan . 06 , 201 6 page 60 of 144 rev .1.00 m4tk series datashee t 5 block diagram numicro ? m4tk block diagram 5.1 figure 5.1 - 1 numicro ? m4 tk block diagram
m4 tk jan . 06 , 201 6 page 61 of 144 rev .1.00 m4tk series datashee t 6 functional descripti on arm ? cortex ? - m4 core 6.1 the cortex ? - m4 processor, a configurable, multistage, 32 - bit risc processor, has three amba ahb - lite interfaces for best parallel performance and includes an nvic component. the processor with optional hardware debug functionality can execute thumb code and is compat ible with other cortex - m profile processors. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. the cortex ? - m4f is a processor with the same capability as the cortex ? - m4 processor and includes floating point arithmetic functionality. the numicro ? m4tk family is embedded with cortex ? - m4f processor. throu ghout this document, the name cortex ? - m4 refers to both cortex ? - m4 and cortex ? - m4f processors. the figure 6.1 - 1 shows the functional controller of the processor. figure 6.1 - 1 cortex ? - m4 block diagram cortex ? - m4 processor features: ? a low gate count processor core, with low latency interrupt processing that has : ? a subset of the thumb instruction set, defined in the armv7 - m architecture reference manual ? banked stack pointer (sp)
m4 tk jan . 06 , 201 6 page 62 of 144 rev .1.00 m4tk series datashee t ? hardware integer divide instructions, sdiv and udiv ? handler and thread mod es ? thumb and debug states ? support for interruptible - continued instructions ldm, stm, push, and pop for low interrupt latency ? automatic processor state saving and restoration for low latency interrupt service routine (isr) entry and exit ? support for armv6 b ig - endian byte - invariant or little - endian accesses ? support for armv6 unaligned accesses ? floating point unit (fpu) in the cortex ? - m4f processor providing: ? 32 - bit instructions for single - precision (c float) data - processing operations ? combined multiply and ac cumulate instructions for increased precision (fused mac) ? hardware support for conversion, addition, subtraction, multiplication with optional accumulate, division, and square - root ? hardware support for denormals and all ie ee rounding modes ? 32 dedicated 32 - bit single precision registers, also addressable as 16 double - word registers ? decoupled three stage pipeline ? nested vectored interrupt controller (nvic) closely integrated with the processor core to achieve low latency interrupt processing. features incl ude: ? external interrupts. configurable from 1 to 240 (the numicro ? m4tk family configured with 64 interrupts) ? bits of priority, configurable from 3 to 8 ? dynamic reprioritization of interrupts ? priority grouping which enables selection of preempting interrupt levels and nonpreempting interrupt levels ? support for tril - chaining and late arrival of interrupts, which enables back - to - back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatic ally saved on interrupt entry, and restored on interrupt exit with on instruction overhead ? support for wake - up interrupt controller (wic) with ultra - low power sleep mode ? memory protection unit (mpu). an optional mpu for memory protection, including: ? eight memory regions ? sub region disable (srd), enabling efficient use of memory regions ? the ability to enable a background region that implements the default memory map attributes ? low - cost debug solution that features: ? debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while sysresetn is
m4 tk jan . 06 , 201 6 page 63 of 144 rev .1.00 m4tk series datashee t asserted. ? serial wire debug port(sw - dp) or serial wire jtag debug port (swj - dp) debug access ? optional flash patch and breakpoint (fpb) unit for implementing breakpoints and code patches ? optional data watchpoint and trace (dwt) unit for implementing watchpoints, data tracing, and system profiling ? optional instrumentation trace macroce ll (itm) for support of printf() style debugging ? optional trace port interface unit (tpiu) for bridging to a trace port analyzer (tpa), including single wire output (swo) mode ? optional embedded trace macrocell (etm) for instruction trace. ? bus interfaces: ? t hree advanced high - performance bus - lite (ahb - lite) interfaces: icode, dcode, and system bus interfaces ? private peripheral bus (ppb) based on advanced peripheral bus (apb) interface ? bit - band support that includes atomic bit - band write and read operations. ? memory access alignment ? write buffer for buffering of write data ? exclusive access transfers for multiprocessor systems
m4 tk jan . 06 , 201 6 page 64 of 144 rev .1.00 m4tk series datashee t system manager 6.2 6.2.1 overview the system manager provides the functions of system control, power modes, wake - up sources, reset sources , system memory map , product id and multi - function pin control . the following sections describe the functions for ? system reset ? power m odes and w ake - up s ources ? system power distributio n ? sram memory organizatio n ? system control r egister for part number id, c hip r eset and m ulti - function p in c ontrol ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control register 6.2.2 system reset the system reset can be issued by one of the events listed below . the se reset event flags can be read from sys_rststs register to determine the reset source . hardware reset can reset chip through peripheral reset signals. software reset can trigger reset through control registers. ? hardware reset sources C power - on reset (por ) C low level on the n reset pin C watchdog time - out reset and window watchdog reset (wdt /wwdt reset) C low voltage reset (lvr) C brown - out detector reset (bod reset) ? software reset sources C chip reset will reset whole chip by writing 1 to chiprst (sys_iprst0[0]) C mc u reset to reboot but keeping the booting setting from aprom or ldrom by writing 1 to sysresetreq (aircr[2]) C cpu reset for cortex? - m4 core only by writing 1 to cpurst (sys_iprst0[1 ])
m4 tk jan . 06 , 201 6 page 65 of 144 rev .1.00 m4tk series datashee t figure 6.2 - 1 system reset s ources l o w v o l t a g e r e s e t p o w e r - o n r e s e t b r o w n - o u t r e s e t r e s e t p u l s e w i d t h 3 . 2 m s w d t / w w d t r e s e t s y s t e m r e s e t ~ 5 0 k o h m @ 5 v r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s n r e s e t v d d a v d d c h i p r e s e t c h i p r s t ( s y s _ i p r s t 0 [ 0 ] ) c p u r e s e t c p u r s t ( s y s _ i p r s t 0 [ 1 ] ) c p u l o c k u p r e s e t m c u r e s e t s y s r s t r e q ( a i r c r [ 2 ] ) l v r e n ( s y s _ b o d c t l [ 7 ] ) b o d r s t e n ( s y s _ b o d c t l [ 3 ] ) p o r o f f ( s y s _ p o r c t l [ 1 5 : 0 ] ) r e s e t p u l s e w i d t h 6 4 w d t c l o c k s r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s g l i t c h f i l t e r 3 6 u s s o f t w a r e r e s e t r e s e t c o n t r o l l e r
m4 tk jan . 06 , 201 6 page 66 of 144 rev .1.00 m4tk series datashee t there are a total of 9 reset sources in the numicro ? family. in general, cpu reset is used to reset cortex - m 4 only; the other reset sources will reset cortex - m 4 and all peripherals. however, there are small differences between each reset source and they are listed in table 6 - 1 . reset sources register por n reset wdt lvr bod lockup chip mcu cpu sys_rststs 0x001 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 8 = 1 bit 0 = 1 bit 5 = 1 bit 7 = 1 chiprst (sys_iprst0[0]) 0x0 - - - - - - - - boden (sys_bodctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 reload from config0 reload from config0 - bodvl (sys_bodctl[2:1]) bodrsten (sys_bodctl[3]) hxten (clk_pwrctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 lxten (clk_pwrctl[1]) 0x0 - - - - - - - - wdtcken (clk_apbclk0[0]) 0x1 - 0x1 - - - 0x1 - - hclksel (clk_clksel0[2:0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdtsel (clk_clksel1[1:0]) 0x3 0x3 - - - - - - - hxtstb (clk_status[0]) 0x0 - - - - - - - - lxtstb (clk_status[1]) 0x0 - - - - - - - - pllstb (clk_status[2]) 0x0 - - - - - - - - hircstb (clk_status[4]) 0x0 - - - - - - - - clksfail (clk_status[7]) 0x0 0x0 - - - - - - - rsten (wdt_ctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - wdten (wdt_ctl[7]) wdt_ctl except bit 1 and bit 7. 0x0700 0x0700 0x0700 0x0700 0x0700 - 0x0700 - -
m4 tk jan . 06 , 201 6 page 67 of 144 rev .1.00 m4tk series datashee t wdt_altctl 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_rldcnt 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_ctl 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 - 0x3f0800 - - wwdt_status 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_cnt 0x3f 0x3f 0x3f 0x3f 0x3f - 0x3f - - bs (fmc_ispctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - bl (fmc_ispctl[16]) fmc_dfba reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 - reload from config1 - - cbs (fmc_ispsts[2:1)) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - mbs ? (fmc_ispsts[3]) pgff (fmc_ispsts[5]) 0x0 - 0x0 - - - 0x0 - - vecmap ? (fmc_ispsts[23: 9]) reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 - reload base on config0 - - other peripheral registers reset value - fmc registers reset value note: - means that the value of register keeps original setting. table 6 - 1 reset value of registers nreset reset 6.2.2.1 the nreset reset means to generate a reset signal by pull ing low nreset pin , which is an asynchronous reset input pin and can be used to reset system at any time. when the nreset voltage is lower than 0.2 v dd and the state keeps longer than 36 us (glitch filter ), c hip will be reset. the nreset reset will control the chip in reset state until the nreset voltage rises above 0.7 v dd and the state keeps longer than 36 us ( glitch filter). the pinrf(sys_rststs[1]) will be set to 1 if the previous reset source is nreset reset. figure 6.2 - 2 shows the nreset reset waveform .
m4 tk jan . 06 , 201 6 page 68 of 144 rev .1.00 m4tk series datashee t figure 6.2 - 2 nreset reset w aveform power - o n reset (por) 6.2.2.2 the power - on reset (por) is used to generate a stable system reset signal and forces the system to be reset when p ower - on to avoid unexpected behavior of mcu. when applying the power to mcu, the por module will detect the rising voltage and generate reset signal to system until the voltage is ready for mcu operation. at por reset, the porf(sys_rststs[0]) will be set to 1 to indicate there is a por reset event. the porf(sys_rststs[0]) bit can be cl eared by writing 1 to it . figure 6.2 - 3 shows the p ower - o n reset waveform. figure 6.2 - 3 power - o n reset (por) w aveform low voltage reset (lvr) 6.2.2.3 if the low voltage reset function is enabled by setting the low voltage reset enable bit lvren (sys_bodctl[7]) to 1, after 200us delay, lvr detection circuit will be stable and the lvr function will be active. then lvr function will detect av dd during system operation. when the av dd voltage is lower than v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]) , c hip will be reset . the lvr reset will control the chip in reset state until the av dd voltage rises above v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]). the pinrf(sys_rststs[1]) will be set to 1 if the previous reset source is nrese t reset. the default setting of low voltage reset is enabled without de - g litch function. figure 6.2 - 4 shows the low voltage reset waveform . n r e s e t 0 . 2 v d d 0 . 7 v d d n r e s e t r e s e t 3 6 u s 3 6 u s v d d v p o r p o w e r - o n r e s e t 0 . 1 v
m4 tk jan . 06 , 201 6 page 69 of 144 rev .1.00 m4tk series datashee t figure 6.2 - 4 low voltage reset (lvr) w aveform brown - out detector reset (bod reset) 6.2.2.4 if the brown - o ut detector (bod) function is enabled by setting the brown - o ut detector enable bit boden (sys_bodctl[0]), brown - out detector function will detect av dd during system operation. when the av dd voltage is lower than v bod and the state keeps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]) , c hip will be reset. the bod reset will control the chip in reset state until the av dd voltage rises above v bod and the state keeps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]) . the default value of boden, bodvl and bodrsten is set by flash controller user configurat ion register cboden (config0 [23]), cbov (config0 [22:21]) and cborst(config0[20]) respectively. user can determine the initial bod setting by setting the config0 register . figure 6.2 - 5 shows the brown - out detector waveform . a v d d v l v r l o w v o l t a g e r e s e t t 1 ( < l v r d g s e l ) t 2 ( = l v r d g s e l ) t 3 ( = l v r d g s e l ) l v r e n 2 0 0 u s d e l a y f o r l v r s t a b l e
m4 tk jan . 06 , 201 6 page 70 of 144 rev .1.00 m4tk series datashee t figure 6.2 - 5 brown - o ut detector (bod) w aveform watch d og timer reset (wdt) 6.2.2.5 in most industr ial applications, system reliability is very important. to automatically recover the mcu from failure status is one way to improve system reliability. the watchdog timer(wdt) is widely used to check if the system works fine. if the mcu is crashed or out of co ntrol, it may cause the watchdog time - out. user may decide to enable system reset during watchdog time - out to recover the system and take action for the system crash/out - of - control after reset. software can check if the reset is caused by watchdog time - ou t to indicate the previous reset is a watchdog reset and handle the failure of mcu after watchdog time - out reset by checking wdtrf(sys_rststs[2]). cpu reset, chip reset and mcu reset 6.2.2.6 the cpu reset means only cortex ? - m4 core is reset and all other peripherals remain the same status after cpu r eset. user can set the cpurst(sys_iprst0[1]) to 1 to assert the cpu reset signal. the chip reset is same with power - on reset. the cpu and all peripherals are reset and bs(fmc_ispctl[1]) bit is automatically reloaded from config setting. user can set the chiprst(sys_iprst0[1]) to 1 to assert the chip reset signal. the mcu reset is similar with chip reset. the difference is that bs(fmc_ispctl[1]) will not be reloaded from config setting and keep its original software setting for booting from aprom or ldrom . user can set the sysresetreq(aircr[2]) to 1 to assert the mcu reset. a v d d v b o d l b o d o u t b o d r s t e n b r o w n - o u t r e s e t t 1 ( < b o d d g s e l ) t 2 ( = b o d d g s e l ) t 3 ( = b o d d g s e l ) h y s t e r e s i s v b o d h
m4 tk jan . 06 , 201 6 page 71 of 144 rev .1.00 m4tk series datashee t 6.2.3 power m odes and wake - up s ources there are several wake - up sources in i dle mode and p ower - down mode. table 6 - 2 lists the available clocks for each power mode. power mode normal m ode idle m ode power - d own m ode definition cpu is in active state cpu is in sleep state cpu is in sleep state and all clocks stop except lxt and lirc. sram content retended. entry condition c hip is in normal mode after system reset released cpu executes wfi instruction. cpu sets sleep mode enable and power down enable and executes wfi instruction. wake - up sources n/a all interrupts rtc, wdt, i2c, timer, uart, bod, gpio, usbh, usbd, otg, can, acmp and tk available clocks all all except cpu clock lxt and lirc after wake - up n/a cpu back to normal mode cpu back to normal mode table 6 - 2 power mode difference table figure 6.2 - 6 power mode state machine n o r m a l m o d e c p u c l o c k o n h x t , h i r c , l x t , l i r c , h c l k , p c l k o n f l a s h o n p o w e r - d o w n m o d e c p u c l o c k o f f h x t , h i r c , h c l k , p c l k o f f f l a s h h a l t s y s t e m r e s e t r e l e a s e d c p u e x e c u t e s w f i i n t e r r u p t s o c c u r i d l e m o d e c p u c l o c k o f f h x t , h i r c , l x t , l i r c , h c l k , p c l k o n f l a s h h a l t 1 . s c r ( s c b [ 2 ] ) = 1 2 . p d _ e n ( p w r c t l [ 7 ] ) = 1 a n d p d w t c p u ( p w r c t l [ 8 ] ) = 1 3 . c p u e x e c u t e s w f i w a k e - u p e v e n t s o c c u r l x t , l i r c o n
m4 tk jan . 06 , 201 6 page 72 of 144 rev .1.00 m4tk series datashee t 1. lxt (32 768 hz xtl) on or off depend s on sw setting in run mode . 2. lirc (10 khz osc) on or off depend s on s/w setting in run mode . 3 . if timer clock source is selected as lirc/lxt and lirc/lxt is on. 4 . if wdt clock source is selected as lirc and lirc is on. 5 . if rtc clock source is selected as lxt and lxt is on. normal mode idle mode power - d own mode hxt ( 4~20 mhz xtl) on on halt hirc (12 /16 mhz osc) on on halt lxt (32 768 hz xtl) on on on/off 1 lirc (10 khz osc) on on on/off 2 pll on on halt ldo on on on cpu on halt halt hclk/pclk on on halt sram retention on on on flash on on halt ebi on on halt gpio on on halt p dma on on halt t i m e r on on on/off 3 pwm on on halt wdt on on on/off 4 wwdt on on halt rtc on on on/off 5 uart on on halt sc on on halt i 2 c on on halt spi on on halt usbh on on halt usbg on on halt otg on on halt can on on halt tk on on halt eadc on on halt dac on on halt
m4 tk jan . 06 , 201 6 page 73 of 144 rev .1.00 m4tk series datashee t acmp on on halt table 6 - 3 c lock s in power modes wake - up sources in p ower - down mode : rtc, wdt, i2c, timer, uart, bod, gpio, usbh, usbd, otg, can, acmp and tk after chip enters power down, the following wake - up sources can wake chip up to n ormal mode . table 6 - 4 list s the c ondition about how to enter p ow er - down mode again for each peripheral. *user needs to wait this condition before setting pd_en(pwrctl[6]) and execute wfi to enter power - down mode . wake - u p source wake - u p c ondition system c an e nter power - d own m ode a gain c ondition * bod brown - out detector interrupt after software writes 1 to clear sys_bodctl[bodif]. gpio gpio interrupt after software write 1 to clear the intsrc [n] bit. timer timer interrupt after software writes 1 to clear twkf ( timer x _intsts [1]) and t i f ( timer x _intsts [0]) . wdt wdt interrupt after software writes 1 to clear wkf ( wdt_ctl [5]) (write protect). rtc alarm interrupt after software writes 1 to clear almif (rtc_intsts[0]) . time tick interrupt after software writes 1 to clear tickif (rtc_intsts[1]) . snoop detection interrupt after software writes 1 to clear snpdif (rtc_intsts[2]) . uart rx data wake - up a fter software writes 1 to clear datwkif ( uart x _intsts [17]). ncts wake - up a fter software writes 1 to clear ctswkif ( uart x _intsts [16]) . i 2 c f alling edge in the i2c_sda or i2c_clk after software writes 1 to clear wkif ( i2c_wksts[0]). usbh remote wake - up after software writes 1 to clear csc (hcrhportstatus1[16]). usb d remote wake - up after software writes 1 to clear busif ( usbd_intsts [0]). otg otg id pin wake - up after software writes 1 to clear otg_intsts[idchgif]. can f alling edge in the can_r x after software writes 0 to clear wakup_sts (can_wu_status [0]). tk wake - up by key touch/release or any key touch after software writes 1 to clear tk_status[tkifx]. acmp comparator power - down wake - up interrupt after software writes 1 to clear acmp_status[wkifx]. table 6 - 4 condition of entering power - down mode again 6.2.4 system power distribution in this chip, power distribution is divided into five segments:
m4 tk jan . 06 , 201 6 page 74 of 144 rev .1.00 m4tk series datashee t ? analog power from av dd and av ss provides the power for analog components operation. the v ref should be connected with an external 1uf capacitor that should be located close to the v ref pin to avoid power noise for analog applications. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from v dd offers th e power for operating the usb transceiver. ? rtc power from v bat provides the power for pf.0~pf.2, rtc and 80 bytes backup registers. ? a dedicated power from v ddio supplies the power for pe.8~pe.13. the outputs of internal voltage regulators, ldo _cap and usb_ vdd33 _cap , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). the figure 6.2 - 7 shows the power distribution of the numicro ? m4tk . figure 6.2 - 7 numicro ? m4tk power distribution diagram u s b t r a n s c e i v e r a v d d a v s s v d d v s s v d d u s b _ d + u s b _ d - v b a t 2 2 . 1 1 8 4 m h z h i r c o s c i l l a t o r 1 0 k h z l i r c o s c i l l a t o r s r a m p l l 5 v t o 3 . 3 v l d o i o c e l l v d d t o 1 . 8 v l d o p o r 5 0 p o r 1 8 t e m p e r a t u r e s e n s o r 4 ~ 2 0 m h z c r y s t a l o s c i l l a t o r 3 2 . 7 6 8 k h z c r y s t a l o s c i l l a t o r d i g i t a l l o g i c f l a s h r t c & 8 0 b y t e s b a c k u p r e g i s t e r p o w e r o n c o n t r o l x 3 2 _ i n ( p f . 1 ) x 3 2 _ o u t ( p f . 0 ) v r e f x t 1 _ o u t x t 1 _ i n g p i o e x c e p t p f . 0 ~ p f . 2 a n d p e . 8 ~ p e . 1 3 1 . 8 v 1 . 8 v 3 . 3 v u s b _ v d d 3 3 _ c a p l d o _ c a p 1 u f 1 u f m 4 5 1 p o w e r d i s t r i b u t i o n v d d i o i o c e l l p e . 8 ~ p e . 1 3 v b a t t o 1 . 8 v l d o i o c e l l t o u c h s e n s o r b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t 1 2 - b i t d a c 1 2 - b i t a d c i n t e r n a l r e f e r e n c e v o l t a g e a n a l o g c o m p a r a t o r p f . 0 ~ p f . 2 1 u f
m4 tk jan . 06 , 201 6 page 75 of 144 rev .1.00 m4tk series datashee t 6.2.5 system memory map the numicro ? m4tk series provides 4g - byte addressing space. the memory locations assigned to each on - chip controllers are shown in the table 6 - 5 . the detailed register definition, memo ry space, and programming will be described in the following sections for each on - chip peripheral. the numicro ? m4tk series only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128kb) ( m4 tk x e only) 0x000 0 _0000 C 0x0003_ffff flash_ba flash memory space (256kb) ( m4 tk x g only) 0x0004_0000 C 0x0005_ffff reserved reserved 0x0006_0000 C 0x0007_ffff reserved reserved 0x2000_0000 C 0x2000_3fff sram0_ba sram memory space 0x2000_4000 C 0x2000_7fff sram1_ba sram memory space 0x2000_8000 C 0x2000_bfff reserved reserved 0x2000_c000 C 0x2000_ffff reserved reserved 0x6000_0000 C 0x6fff_ffff extmem_ba external memory space for ebi interface (256 mb) peripheral controllers space (0x4000_0000 C 0x400f_ffff) 0x4000_0000 C 0x4000_01ff sys_ba system control registers 0x4000_0200 C 0x4000_02ff clk_ba clock control registers 0x4000_ 03 00 C 0x4000_ 03 ff nmi _ba nmi control registers 0x4000_4000 C 0x4000_4fff gpio_ba gpio control registers 0x4000_8000 C 0x4000_8fff pdma_ba peripheral dma control registers 0x4000_9000 C 0x4000_9fff usbh_ba usb host control registers 0x4000_b000 C 0x4000_bfff reserved reserved 0x4000_c000 C 0x4000_cfff fmc_ba flash memory control registers 0x4000_d000 C 0x4000_dfff reserved reserved 0x4001_0000 C 0x4001_0fff ebi_ba external bus interface control registers 0x4001_9000 C 0x4001_9fff reserved reserved 0x4003_0000 C 0x4003_0fff reserved reserved 0x4003_1000 C 0x4003_1fff crc_ba crc generator registers 0x5000_8000 C 0x5000_ffff reserved reserved apb controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4004_0000 C 0x4004_0fff wdt_ba watchdog timer control registers 0x4004_1000 C 0x4004_1fff rtc_ba real time clock (rtc) control register 0x4004_3000 C 0x4004_3fff eadc_ba enhanced analog - digital - converter (eadc) control registers 0x4004_4000 C 0x4004_4fff reserved reserved 0x4004_5000 C 0x4004_5fff acmp01_ba analog comparator 0/ 1 control registers
m4 tk jan . 06 , 201 6 page 76 of 144 rev .1.00 m4tk series datashee t 0x4004_6000 C 0x4004_6fff reserved reserved 0x4004_7000 C 0x4004_7fff dac_ba dac control registers 0x4004_8000 C 0x4004_8fff reserved reserved 0x4004_9000 C 0x4004_9fff reserved reserved 0x4004_d000 C 0x4004_dfff otg_ba usb otg control register 0x4005_0000 C 0x4005_0fff tmr01_ba timer0/timer1 control registers 0x4005_1000 C 0x4005_1fff tmr23_ba timer2/timer3 control registers 0x4005_8000 C 0x4005_8fff pwm 0 _ba pwm0 control registers 0x4005_9000 C 0x4005_9fff pwm1_ba pwm1 control registers 0x4005_c000 C 0x4005_cfff reserved reserved 0x4005_d000 C 0x4005_dfff reserved reserved 0x4006_0000 C 0x4006_0fff spi0_ba spi0 control registers 0x4006_1000 C 0x4006_1fff spi1_ba spi1 control registers 0x4006_2000 C 0x4006_2fff spi2_ba spi2 control registers 0x4006_3000 C 0x4006_3fff reserved reserved 0x4007_0000 C 0x4007_0fff uart0_ba uart0 control registers 0x4007_1000 C 0x4007_1fff uart1_ba uart1 control registers 0x4007_2000 C 0x4007_2fff uart2_ba uart2 control registers 0x4007_3000 C 0x4007_3fff uart3_ba uart3 control registers 0x4007_4000 C 0x4007_4fff reserved reserved 0x4007_5000 C 0x4007_5fff reserved reserved 0x4008_0000 C 0x4008_0fff i2c0_ba i 2 c0 control registers 0x4008_1000 C 0x4008_1fff i2c1_ba i 2 c1 control registers 0x4008_2000 C 0x4008_2fff reserved reserved 0x4008_3000 C 0x4008_3fff reserved reserved 0x4008_4000 C 0x4008_4fff reserved reserved 0x4009_0000 C 0x4009_0fff sc0_ba smartcard host 0 control registers 0x4009_1000 C 0x4009_1fff reserved reserved 0x4009_2000 C 0x4009_2fff reserved reserved 0x4009_3000 C 0x4009_3fff reserved reserved 0x4009_4000 C 0x4009_4fff reserved reserved 0x4009_5000 C 0x4009_5fff reserved reserved 0x400a_0000 C 0x400a_0fff can0_ba can0 bus control registers 0x400a_1000 C 0x400a_1fff reserved reserved 0x400b_0000 C 0x400b_0fff reserved reserved
m4 tk jan . 06 , 201 6 page 77 of 144 rev .1.00 m4tk series datashee t 0x400b_1000 C 0x400b_1fff reserved reserved 0x400b_0000 C 0x400b_0fff reserved reserved 0x400b_1000 C 0x400b_1fff reserved reserved 0x400c_0000 C 0x400c_0fff usbd _ba usb device control register 0x400e_0000 C 0x400e_0fff reserved reserved 0x400e_2000 C 0x400e_2fff tk_ba touch key control registers 0x5008_0000 C 0x5008_0fff reserved reserved system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers table 6 - 5 address space assignments for on - chip controllers
m4 tk jan . 06 , 201 6 page 78 of 144 rev .1.00 m4tk series datashee t 6.2.6 sram memory org a n iz ation the m4tk supports embedded sram with total 32 k b size and the sram organization is separated to two banks: sram bank0 and sram bank1. each of these two banks has 16 k b address spa ce and can be accessed simultaneously. the sram bank0 supports parity error check to make sure chip operating more stable. ? supports total 32 k b sram ? supports byte / half word / word write ? supports fixed 16 k b sram bank for independent access ? supports parity error check function for sram bank0 ? supports oversize response error ? supports remap address to 0x1000_0000 figure 6.2 - 8 sram block diagram a h b b u s a h b i n t e r f a c e c o n t r o l l e r s r a m d e c o d e r s r a m b a n k 0 s r a m b a n k 1 s r a m d e c o d e r a h b i n t e r f a c e c o n t r o l l e r
m4 tk jan . 06 , 201 6 page 79 of 144 rev .1.00 m4tk series datashee t figure 6.2 - 9 shows the sram organization of m4tk . there are two sram banks in m4tk and each bank is addressed to 16 k b . the bank0 address space is from 0x2000_0000 to 0x2000_3fff. the bank 1 address space is from 0x2000_4000 to 0x2000_7fff. the address between 0x2000_8000 to 0x3fff_ffff is illegal memory space and chip will enter hardfault if cpu accesses these illegal memory addresses. the address of each bank is remapping from 0x2000_0000 to 0x1000_0000. cpu can read sram bank0 through 0x2000_0000 to 0x2000_3fff or 0x1000_0000 to 0x1000_3fff, and read sram bank1 through 0x2000_4000 to 0x2000_7fff or 0x1000_4000 to 0x1000_7fff . figure 6.2 - 9 sram memory organization 5 1 2 m b 1 6 k b s r a m b a n k 0 0 x 2 0 0 0 _ 0 0 0 0 r e s e r v e d 0 x 3 f f f _ f f f f 1 6 k b s r a m b a n k 1 0 x 2 0 0 0 _ 3 f f f 0 x 2 0 0 0 _ 7 f f f 0 x 2 0 0 0 _ 4 0 0 0 0 x 2 0 0 0 _ 8 0 0 0 3 2 k b d e v i c e 1 6 k b s r a m b a n k 0 0 x 1 0 0 0 _ 0 0 0 0 1 6 k b s r a m b a n k 1 0 x 1 0 0 0 _ 3 f f f 0 x 1 0 0 0 _ 7 f f f 0 x 1 0 0 0 _ 4 0 0 0 3 2 k b d e v i c e r e m a p p i n g r e m a p p i n g
m4 tk jan . 06 , 201 6 page 80 of 144 rev .1.00 m4tk series datashee t sram bank0 has byte parity error check function. when cpu is accessing sram bank0, the parity error checking mechanism is dynamic operating. as parity error occurred , the perrif (sys_sram_status[0]) will be asserted to 1 and the sys_sram_erraddr register will recode the address with parity error. chip will enter interrupt when sram parity error occurred if perrien (sys_sram_intctl[0]) is set to 1. when sram parity err or occurred , chip will stop detecting sram parity error until user writes 1 to clear the perrif (sys_sram_status[0]) bit.
m4 tk jan . 06 , 201 6 page 81 of 144 rev .1.00 m4tk series datashee t 6.2.7 system timer (systick) the cortex ? - m4 includes an integrated system timer, systick, which provides a simple, 24 - bit clear - on - write, d ecrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current va lue register (syst_val) to zero, and reload (wrap) to the value in the systick reload value register (syst_load) on the next clock cycle, and then decrement on subsequent clocks. when the counter transitions to zero, the countflag status bit is set. the co untflag bit clears on reads. the syst_val value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_load value rather than an arbitrary value when it is enabled. if the syst_load is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, p lease refer to the arm ? cortex? - m4 technical reference manual and arm ? v6 - m architecture reference manual . 6.2.8 nested vectored interrupt controller (nvic) the nvic and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. the nvic maintains knowledge of the stacked, or nested, interrupts to enable tail - chaining of interrupts. you can only fully access the nvic from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable the configuration and control register. any other user mode access causes a bus fault. you can access all nvic registers using byte, halfword, and word accesses unless otherwise stated. nvic registers ar e located within the scs (system control space). all nvic registers and system debug registers are little - endian regardless of the endianness state of the processor. the nvic supports: ? an implementation - defined number of interrupts, in the range 1 - 240 interrupts. ? a progra mmable priority level of 0 - 1 5 for each interrupt ; a higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ? level and pulse detection of interrupt signals. ? dynamic reprioritization of interrupts. ? grou ping of priority values into group priority and subpriority fields. ? interrupt tail - chaining. ? an external non maskable interrupt (nmi) ? wic with u ltra - low p ower s leep mode support the processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. this provides low latency exception handling.
m4 tk jan . 06 , 201 6 page 82 of 144 rev .1.00 m4tk series datashee t clock controller 6.3 6.3.1 overview the clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. the clock c ontroller also implements the power control function with the individually clock on/off control, clock source selection and a clock divider. the chip will not enter power - down mode until cpu sets the p ower - down enable bit pden (clk_pwrctl[7]) and cortex ? - m4 core executes the wfi instruction. after that, chip enters power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. in power - down mode, the clock controller turns off the 4~20 mhz external high speed crystal (hxt) and 22.1 184 mhz internal high speed rc oscillator (hirc) to reduce the overall system power consumption. the figure 6.3 - 1 show s the clock generator and the overview of the clo ck source control.
m4 tk jan . 06 , 201 6 page 83 of 144 rev .1.00 m4tk series datashee t figure 6.3 - 1 clock generator global view diagram 1 0 c l k _ p l l c t l [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k _ c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k u a r t 0 - 3 p d m a a c m p 0 1 i 2 c 0 r t c f m c w d t p w m 0 t m r 0 t m r 1 c p u e b i 3 2 . 7 6 8 k h z 1 0 k h z 1 1 1 0 1 0 0 0 1 0 0 0 p c l k 0 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z 0 0 0 c l k _ c l k s e l 0 [ 2 : 0 ] s y s t _ c t r l [ 2 ] c p u c l k 1 / ( h c l k d i v + 1 ) p c l k 1 c p u c l k h c l k 2 2 . 1 1 8 4 m h z c l k _ c l k s e l 1 [ 1 0 : 8 ] c l k _ c l k s e l 1 [ 1 4 : 1 2 ] 1 0 p l l f o u t p c l k 0 c l k _ c l k s e l 2 [ 0 ] 2 2 . 1 1 8 4 m h z 1 0 k h z 1 0 k h z 1 1 1 0 c l k _ c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t d i v + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z c a n 0 0 1 3 2 . 7 6 8 k h z 1 0 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z c l k _ c l k s e l 1 [ 2 5 : 2 4 ] 1 1 1 2 2 . 1 1 8 4 m h z 1 0 1 1 0 k h z 0 1 1 t 0 ~ t 1 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z c l k _ c l k s e l 1 [ 2 9 : 2 8 ] 1 1 1 0 0 1 0 0 u s b 1 / ( u s b d i v + 1 ) p l l f o u t s p i 2 p c l k 0 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z p l l f o u t c l k _ c l k s e l 2 [ 3 : 2 ] c l k _ c l k s e l 2 [ 7 : 6 ] 1 1 1 0 0 1 0 0 1 0 3 2 . 7 6 8 k h z c l k _ c l k s e l 3 [ 8 ] s c 0 p c l k 0 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z p l l f o u t c l k _ c l k s e l 3 [ 1 : 0 ] 1 1 1 0 0 1 0 0 e a d c 1 / ( e a d c d i v + 1 ) p c l k 1 b o d 1 0 k h z 1 / ( s c 0 d i v + 1 ) c r c d a c w w d t 1 0 k h z 1 1 1 0 c l k _ c l k s e l 1 [ 3 1 : 3 0 ] h c l k 1 / 2 0 4 8 s p i 0 c l o c k o u t p u t p c l k 0 i 2 c 1 t m r 2 t m r 3 1 1 1 0 1 0 0 0 1 0 0 0 p c l k 1 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k _ c l k s e l 1 [ 1 8 : 1 6 ] c l k _ c l k s e l 1 [ 2 2 : 2 0 ] 1 0 1 1 0 k h z 0 1 1 t 2 ~ t 3 p c l k 1 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z p l l f o u t c l k _ c l k s e l 2 [ 5 : 4 ] 1 1 1 0 0 1 0 0 s p i 1 p w m 1 1 0 p l l f o u t p c l k 1 c l k _ c l k s e l 2 [ 1 ] 2 2 . 1 1 8 4 m h z 1 1 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
m4 tk jan . 06 , 201 6 page 84 of 144 rev .1.00 m4tk series datashee t 6.3.2 clock generator the clock generator consists of 5 clock sources, which are listed below: ? 32.768 khz external low speed crystal oscillator ( l xt) ? 4~20 mhz external high speed crystal oscillator (hxt) ? programmable pll output clock frequency ( pllfout ), pll source can be selected from external 4~20 mhz external high speed crystal (hxt) or 22.1184 mhz internal high speed oscillator (hirc) ? 22.1184 mhz internal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc) figure 6.3 - 2 clock generator block diagram x t 1 _ o u t e x t e r n a l 4 ~ 2 4 m h z c r y s t a l ( h x t ) h x t e n ( c l k _ p w r c t l [ 0 ] ) x t 1 _ i n i n t e r n a l 2 2 . 1 1 8 4 m h z o s c i l l a t o r ( h i r c ) h i r c e n ( c l k _ p w r c t l [ 2 ] ) 0 1 p l l p l l s r c ( c l k _ p l l c t l [ 1 9 ] ) p l l f o u t x 3 2 _ o u t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l ( l x t ) l x t l x t e n ( c l k _ p w r c t l [ 1 ] ) x 3 2 _ i n i n t e r n a l 1 0 k h z o s c i l l a t o r ( l i r c ) l i r c e n ( c l k _ p w r c t l [ 3 ] ) h x t h i r c l i r c
m4 tk jan . 06 , 201 6 page 85 of 144 rev .1.00 m4tk series datashee t 6.3.3 system clock and systick clock the system clock has 5 clock sources, which were generated from clock generator block. the clock source switch depends on the register hclk sel (clk_clksel0[2:0]). the block diagram is shown in the figure 6.3 - 3 . figure 6.3 - 3 system clock block diagram there are two clock fail detectors to observe hxt and lxt clock source and they have individual enable and interrupt control. when hxt detector is enabled, the hirc clock is enabled automatically. when lxt detector is enabled, the lirc clock is enabled automatically. when hxt cloc k detector is enabled, the system clock will auto switch to hirc if hxt clock stop being detected on the following condition: system clock source comes from hxt or system clock source comes from pll with hxt as the input of pll. if hxt clock stop condition is detected, the hxtfif (clk_clkdsts[0]) is set to 1 and chip will enter interrupt if hxtfie (clk_clkdctl[5]) is set to 1. user can trying to recover hxt by disable hxt and enable hxt again to check if the clock stable bit is set to 1 or not. if hxt clock stable bit is set to 1, it means hxt is recover to oscillate after re - enable action and user can switch system clock to hxt again. the hxt clock stop detect and system clock switch to hirc procedure is shown in the figure 6.3 - 4 . 0 1 1 0 1 0 0 0 1 p l l f o u t l x t h x t l i r c h c l k s e l ( c l k _ c l k s e l 0 [ 2 : 0 ] ) h i r c 0 0 0 1 / ( h c l k _ n + 1 ) h c l k d i v ( c l k _ c l k d i v 0 [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b 1 c p u c l k h c l k p c l k 1 1 1 1 1 / ( h c l k _ n + 1 ) 1 / ( h c l k d i v + 1 ) a p b 0 p c l k 0 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
m4 tk jan . 06 , 201 6 page 86 of 144 rev .1.00 m4tk series datashee t figure 6.3 - 4 hxt stop protect p rocedure the clock source of systick in cortex ? - m4 core can use cpu clock or external clock (syst_ ctrl [2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk sel (clk_clksel0[5:3]). the block diagram is shown in the figure 6.3 - 5 . figure 6.3 - 5 systick clock control block diagram 6.3.4 peripherals clock the peripherals clock ha s different clock source switch setting, which depends on the different peripheral. please refer to the clk_clksel1 and clk_clksel2 register description in 5.3. 8 . s e t h x t f d e n t o e n a b l e h x t c l o c k d e t e c t o r h x t f i f = 1 ? s y s t e m c l o c k s o u r c e = h x t o r p l l w i t h h x t ? y e s s y s t e m c l o c k k e e p o r i g i n a l c l o c k n o y e s s w i t c h s y s t e m c l o c k t o h i r c n o 1 1 1 0 1 1 0 1 0 0 0 1 h x t l x t h x t h c l k s t c l k s e l ( c l k _ c l k s e l 0 [ 5 : 3 ] ) s t c l k h i r c 0 0 0 1 / 2 1 / 2 1 / 2 n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
m4 tk jan . 06 , 201 6 page 87 of 144 rev .1.00 m4tk series datashee t 6.3.5 power - down mode clock when entering power - down mode, system clocks, some clock sources and som e peripheral clocks are disabled. some clock sources and peripherals clock are still active in power - down mode. for theses clocks, which still keep active, are listed below: ? clock generator ? 10 khz internal low speed rc oscillator (lirc ) clock ? 32.768 khz ex ternal low speed crystal oscillator ( l xt ) clock ? peripherals clock (when the module s adopt lxt or lirc as clock source) 6.3.6 clock output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where f in is input clock frequency to the cl ock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in freqsel (clk_clkoctl[3:0]). when writing 1 to clkoen (clk_clkoctl[4]), the chained counter starts to count. when writing 0 to clkoen (clk_clkoctl[4]), the chained counter continuously runs till divided clock reaches low state and stay s in low state. figure 6.3 - 6 clock source of clock output 1 1 1 0 0 1 0 0 h c l k l x t h x t h i r c c l k o s e l ( c l k _ c l k s e l 1 [ 2 9 : 2 8 ] ) c l k o c k e n ( c l k _ a p b c l k 0 [ 6 ] ) c l k o _ c l k n o t e : b e f o r e c l o c k s w i t c h i n g , b o t h t h e p r e - s e l e c t e d a n d n e w l y s e l e c t e d c l o c k s o u r c e s m u s t b e t u r n e d o n a n d s t a b l e .
m4 tk jan . 06 , 201 6 page 88 of 144 rev .1.00 m4tk series datashee t figure 6.3 - 7 clock output block diagram 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f r e q s e l ( c l k _ c l k o c t l [ 3 : 0 ] ) c l k o 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r c l k o e n ( c l k _ c l k o c t l [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r 0 1 d i v i d e r 1 * ( f r q d i v [ 5 ] ) c l k o _ c l k 0 1 c l k 1 h z e n ( c l k _ c l k o c t l [ 6 ] ) 1 h z c l o c k f r o m r t c 0 1 l x t l i r c r t c s e l ( c l k _ c l k s e l 3 [ 8 ] ) / 3 2 7 6 8
m4 tk jan . 06 , 201 6 page 89 of 144 rev .1.00 m4tk series datashee t flash memeory controller (fmc) 6.4 6.4.1 overview the numicro ? m4tk series is equipped with 128/256 kb on - chip embedded flash for application and configurable data flash to store some application dependent data. a user configuration block provides for system initiation. a 4 k b loader rom (ldrom) is used for in - system - programming (isp) function. a 16k b boot loader consists of native isp functions. a 4kb cache with zero wait cycle is used to improve flash access performance. this chip also supports in - application - programming (iap) function, user switches the code executing without the chip reset after the emb edded flash updated. 6.4.2 features ? supports 128/256 k b a pplication rom (aprom) . ? supports 4 k b l oader rom (ldrom) . ? supports d ata f lash with configurable memory size. ? supports 8 bytes user configuration block to control system initiation. ? supports 2 k b page erase for all embedded flash. ? supports boot loader with native in - system - program ming (isp) functions. ? supports 32 - bit/64 - bit and multi - word flash programming function. ? supports fast flash programming verification function. ? supports checksum calculat ion function. ? supports in - system - program ming (isp) / in - application - program ming (iap) to update embedded flash memory. ? supports cache memory to improve flash access performance and reduce power consumption.
m4 tk jan . 06 , 201 6 page 90 of 144 rev .1.00 m4tk series datashee t external bus interface (ebi) 6.5 6.5.1 overview the numicro ? m4tk is equip ped with an external bus interface (ebi) for external device used. to save the connections between external device and the numicro ? m4tk , ebi operating at address bus and data bus multiplex mode. the ebi supports two chip selects that can connect two external devices with different timing setting requirement. 6.5.2 features the external bus interface (ebi) has the following functions: ? supports a ddress bus and data bus multiplex mode to save the address pins ? supports two chip selects with polarity control ? supports e xternal devices with max. 1 m b size for each chip select ? supports v ariable external bus base clock (mclk) which based on hclk ? supports 8 - bit or 16 - bit data width for each chip select ? supports v ariable address latch enable time (tale ) ? supports v ariable data access time (tacc) and data access hold time (tahd) for each chip select ? supports c onfigurable idle cycle for different access condition: idle of write command finish (w2x) and idle of read - to - read (r2r)
m4 tk jan . 06 , 201 6 page 91 of 144 rev .1.00 m4tk series datashee t general purpose i/o (gpio) 6.6 6.6.1 overview the numicro ? m4tk series has up to 87 general purpose i/o pins to be shared with other function pins depending on the chip configuration. these 87 pins are arranged in 6 ports named as pa, pb, pc, pd, pe and pf. pa, pb, pc, and pd has 16 pi ns on port. pe has 15 pins on port.pf has 8 pins on port. each of the 87 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, push - pull output, open - drain output or quasi - bidirectional mode. after the chip is reset, the i/o mode of all pins are depending on cioin (config0[10]). each i/o pin has a very weakly individual pull - up resistor which is about 110 k ? ~ 300 k ? for v d d is from 5.0 v to 2.5 v. 6.6.2 features ? four i/o modes: ? quasi - bidirectional mode ? push - pull output mode ? open - drain output mode ? input only with high impendence mode ? ttl/schmitt trigger input selectable ? i/o pin can be configured as interrupt source with edge/level setting ? supports high drive and high slew rate i/o mode ? configurable default i/o mode of all pins after reset by cioini (config0[10]) setting ? cioin = 0, all gpio pins in quasi - bidirectional mode after chip reset ? cioin = 1, all gpio pins in input mode after chip reset ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling the pin interrupt function will also enable the wake - up function ? supports 5v - tolerance function for following pins ? pa.0 ~ pa.15, pc.0 ~ pc.7, pc.9 ~ pc.15, pd.5 ~ pd. 8, pd. 10 ~ pd.15, pe.0 ~ pe.14, pf.2, pf.5 ~ pf.6 ? pa.0 ~ pa.15, pb.14 ~ pb.14, pc.0 ~ pc. 8 , pc. 10 ~ pc.1 3 , pd. 4 ~ pd. 7 , pd.12 ~ pd.15, pe.0 ~ pe.1, pe.3 ~ pe.5, pe.8 ~ pe.1 3 , pf.2 .
m4 tk jan . 06 , 201 6 page 92 of 144 rev .1.00 m4tk series datashee t pdma controller (pdma) 6.7 6.7.1 overview the peripheral direct memory access (pdma) controller is used to provide high - speed data transfer. the pdma controller can transfer data from one address to another without cpu intervention. this has the benefit of reducing the workload of cpu and keeps cpu resources free for other applications. the pdma controller has a total of 12 channels and each channel can perform transfer between memory and peripherals or between memory and memory. 6.7.2 features ? supports 12 independently configurable channels ? sup ports selectable 2 level of priority (fixed priority or round - robin priority) ? supports transfer data width of 8, 16, and 32 bits ? supports source and destination address increment size can be byte, half - word, word or no increment ? supports software and spi, uart, dac, adc and pwm request ? supports scatter - gather mode to perform sophisticated transfer through the use of the descript or link list table ? supports single and burst transfer type
m4 tk jan . 06 , 201 6 page 93 of 144 rev .1.00 m4tk series datashee t timer controller (tmr) 6.8 6.8.1 overview the timer controller includes four 32 - bit timers, timer0 ~ timer3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external inpu t pins, and interval measurement by external capture pins. 6.8.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle - output and continuous counting operation modes ? 24 - bit up counter value is readable through cnt ( timerx_cnt[23:0] ) ? support s event counting function ? 24 - bit capture value is readable through capdat ( timerx_cap[23:0] ) ? supports external capture pin event f or interval measurement ? supports ex ternal capture pin event to reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated ? support timer0 time - out interrupt signal to trigger touch - key scan ? support timer0 ~ timer3 time - out interrupt signal or capture interrupt signal to trigger pwm, eadc and dac function
m4 tk jan . 06 , 201 6 page 94 of 144 rev .1.00 m4tk series datashee t pwm generator and capture timer (pwm) 6.9 6.9.1 overview the m4tk provides two pwm generators pwm0 and pwm1 as e` ! ??? . each pwm supports 6 channels of pwm output or input capture. there is a 12 - bit prescaler to support flexible clock to the 16 - bit pwm counter with 16 - bit comparator. the pwm counter supports up, down and up - do wn counter types. pwm using comparator compared with counter to generate events. these events use to generate pwm pulse, interrupt and trigger signal for eadc/dac to start conversion. the pwm generator supports two standard pwm output modes: independent mode and complementary mode, they have difference architecture. there are two output functions based on standard output modes: group function and synchronous function. group function can be enabled under independent mode or complementary mode. synchronous function only enabled under complementary mode. complementary mode has two comparators to generate various pwm pulse with 12 - bit dead - time generator and another free trigger comparator to generate trigger signal for eadc. for pwm output control unit, it su pports polarity output, independent pin mask and brake functions. the pwm generator also supports input capture function. it supports latch pwm counter value to corresponding register when input channel has a rising transition, falling transition or both t ransition is happened. capture function also support pdma to transfer captured data to memory. 6.9.2 features pwm function features 6.9.2.1 ? supports maximum clock frequency up to144mhz ? supports up to two pwm modules, each module provides 6 output channels. ? supports independent mode for pwm output/capture input channel ? supports complementary mode for 3 complementary paired pwm output channel ? dead - time insertion with 12 - bit resolution ? synchronous function for phase control ? two compared values during one period ? supports 12 - bit pre - scalar from 1 to 4096 ? supports 16 - bit resolution pwm counter ? up, down and up/down counter operation type ? supports one - shot or auto - reload counter operation mode ? supports group function ? supports synchronous function ? supports mask function and tr i - state enable for each pwm pin ? supports brake function ? brake source from pin, analog comparator and system safety events (clock failed, sram parity error, brown - out detection and cpu lockup). ? noise filter for brake source from pin ? edge detect brake source to control brake state until brake interrupt cleared
m4 tk jan . 06 , 201 6 page 95 of 144 rev .1.00 m4tk series datashee t ? level detect brake source to auto recover function after brake condition removed ? supports interrupt on the following events: ? pwm counter match zero, period value or compared value ? brake condition happened ? supports trigger eadc/dac on the following events: ? pwm counter match zero, period value or compared value ? pwm counter match free trigger comparator compared value (only for eadc) capture function features 6.9.2.2 ? supports up to 12 c apture input channels with 16 - bit resolution ? supports rising or falling capture condition ? supports input rising/falling capture interrupt ? supports rising/falling capture with counter reload option ? supports pdma transfer function for pwm all channels
m4 tk jan . 06 , 201 6 page 96 of 144 rev .1.00 m4tk series datashee t watchdog timer (wdt) 6.10 6.10.1 overview the purpose of watchdog timer (wdt) is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to w ake - up system from idle/power - down mode. 6.10.2 features ? 18 - bit free running up counter for wdt time - out interval ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 1.6 ms ~ 26. 214 s if wdt_clk = 10 khz . ? system kept in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable wdt reset delay period, including 1026 130 18 or 3 wdt_clk reset delay period ? supports to force wdt enabled after chip powered on or reset by setting cwdten[2:0] in config0 register ? supports wdt time - out wake - up fu nction only if wdt clock source is selected as lirc or lxt.
m4 tk jan . 06 , 201 6 page 97 of 144 rev .1.00 m4tk series datashee t window watchdog timer (wwdt) 6.11 6.11.1 overview the window watchdog timer (wwdt) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 features ? 6 - bit down counter value (cntdat) and 6 - bit compare value (cmpdat) to make the wwdt time - out window period flexible ? supports 4 - bit value (pscsel) to programmable maximum 11 - bit prescale counte r period of wwdt counter
m4 tk jan . 06 , 201 6 page 98 of 144 rev .1.00 m4tk series datashee t real time clock (rtc) 6.12 6.12.1 overview the real time clock (rtc) controller provides the real time and calendar message. the rtc offers programmable time tick and alarm match interrupts. the data format of time and calendar messages are ex pressed in bcd format. a digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. the rtc controller also offers 80 bytes spare registers to store users important information. the spare registers content is cleared when specified event on tamper pin is detected. 6.12.2 features ? supports real time counter in rtc_time (hour , minute , second) and calendar counter in rtc_cal (year , month , day) for rtc time and calendar check ? supports alarm time (hour , minut e , second ) and calendar (year , month , day) settings in rtc_talm and rtc_calm ? supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in rtc_tamsk and rtc_camsk ? selectable 12 - hour or 24 - hour time scale in rtc_clkfmt register ? supports leap y ear indication in rtc_leapyear register ? supports day of the w eek counter in rtc_weekday register ? frequency of rtc clock source compensate by rtc_freqadj register ? all time and calendar message expressed in bcd format ? support s periodic rtc t ime t ick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? support s rtc time tick and alarm match interrupt ? support s chip wake - up from idle or p ower - down mode while a rtc interrupt signal is generated ? supports 80 bytes spare registers and a snoop pin detection to clear the content of these spare registers
m4 tk jan . 06 , 201 6 page 99 of 144 rev .1.00 m4tk series datashee t uart interface controller (uart) 6.13 6.13.1 overview the numicro ? m4tk series provides four channels of universal asynchronous receiver/transmitters (uart). uart controller performs normal speed uart and supports flow control function. the uart controller performs a serial - to - parallel conversion on data received from the per ipheral and a parallel - to - serial conversion on data transmitted from the cpu. each uart controller channel supports ten types of interrupts. the uart controller also supports irda sir, rs - 485 and auto - baud rate measuring function. 6.13.2 features ? full - duplex asyn chronous communications ? separate s receive and transmit 16/16 bytes entry fifo for data payloads ? support s hardware auto - flow control ? programmable receiver buffer trigger level ? support s programmable baud rate generator for each channel individually ? support s n cts and rx data wake - up function ? support s 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting dly ( uart_tout [ 15:8 ] ) ? supports auto - baud rate measurement ? support s break error, frame error, parity error and receiv e/ transmit buffer overflow detect ion function ? fully programmable serial - interface characteristics ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation ? support s irda sir function mode ? supports for 3/16 bit duration for normal mode ? support s lin function mode ( only uart0 /uart1 with lin function) ? sup ports lin master/slave mode ? supports programmable break generation function for transmitter ? supports break detection function for receiver ? support s rs - 485 function mode ? supports rs - 485 9 - bit mode ? supports hardware or software enables to program nrts pin to control rs - 485 transmission direction uart feature uart0 / uart1 uart2 / uart3 sc _ uart fifo 16 byte s 16 bytes 4 bytes
m4 tk jan . 06 , 201 6 page 100 of 144 rev .1.00 m4tk series datashee t auto flow control (cts/rts) - irda - lin - - rs - 485 f unction m ode - auto - flow control - ncts w ake - u p - rx data w ake - up - auto - baud rate m easurement - stop bit length 1, 1.5, 2 bit 1, 1.5, 2 bit 1, 2 bit word length 5, 6,7, 8 bits e ven / o dd p arity s tick b it - = supported table 6 - 6 numicro ? m4tk s eries uart feature
m4 tk jan . 06 , 201 6 page 101 of 144 rev .1.00 m4tk series datashee t smart card host interface (sc) 6.14 6.14.1 overview the smart card interface controller (sc controller) is based on iso/intenc 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. 6.14.2 features ? iso - 7816 - 3 t = 0, t = 1 compliant. ? emv2000 compliant ? one iso - 7816 - 3 port ? separates receive/transmit 4 byte entry fifo for data payloads. ? programmable transmission clock frequency. ? programmable receiver buffer trigger level. ? programmable guard time selection (11 etu ~ 267 etu). ? a 24 - bit and two 8 - bit timers for answer to request (atr) and waiting times processing. ? supports auto inverse convention function. ? supports transmitter and receiver error retry and error number limiting function. ? supports hardware activation sequence, hardware warm reset sequence and hardware ? deactivation sequence process. ? supports hardware auto deactivation sequence when detected the card removal. ? supports uart mode ? full duplex, asyn chronous communications. ? separates receiving / transmitting 4 bytes entry fifo for data payloads. ? supports programmable baud rate generator. ? supports programmable receiver buffer trigger level. ? programmable transmitting data delay time between the last sto p bit leaving the tx - fifo and the de - assertion by setting egt (sc_egt[7:0]). ? programmable even, odd or no parity bit generation and detection. ? programmable stop bit, 1 - or 2 - stop bit generation
m4 tk jan . 06 , 201 6 page 102 of 144 rev .1.00 m4tk series datashee t i 2 c serial interface controller (i 2 c) 6.15 6.15.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more mast ers attempt to control the bus simultaneously. there are two sets of i 2 c controller which supports bus management (system management (sm)/power management (pm) bus compatible) and power - down wake - up function. 6.15.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the i 2 c bus include: ? supports up to two i 2 c ports ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices with different bit rates to communicate via one serial bus ? built - in 14 - bit time - out counter requesting the i 2 c i nterrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four slave address with mask option) ? supports bus management (sm/p m compatible) function ? supports power - down wake - up function
m4 tk jan . 06 , 201 6 page 103 of 144 rev .1.00 m4tk series datashee t serial peripheral interface (spi) 6.16 6.16.1 overview the serial peripheral interface (spi) applies to synchronous serial data communication and allows full duplex transfer. devices communicate in master/slave mode with the 4 - wire bi - direction interface. the numicro ? m4tk series contains up to three sets of s pi controllers performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. each spi controller can be configured as a master or a slave device. spi 0 c ontroller supports 2 - bit transfer mode to perform full - duplex 2 - bit data transfer and also supports dual and quad i/o transfer mode. spi 1 and spi2 controller also support i 2 s mode to connect external audio codec. 6.16.2 features ? spi mode ? up to three sets of spi controllers ? supports master or slave mode operation ? supports 2 - bit transfer mode ? supports dual and quad i/o transfer mode for spi0 ? configurable bit length of a transaction word from 8 to 32 - bit ? provides separate 4 - /8 - level depth transmit and receive fifo buffers ? supports msb first or lsb first transfer sequence ? supports byte reorder function ? supports pdma transfer ? supports 3 - wire, no slave selection signal, bi - direction interface ? i 2 s mode for spi1 and spi2 ? supports m aster or s lave ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes ? provides separate 4 - level depth transmit and receive fifo buffers ? supports monaural and stereo audio data ? supports pcm mode a, pcm mode b, i 2 s and msb justified data format ? supports pdma transfer
m4 tk jan . 06 , 201 6 page 104 of 144 rev .1.00 m4tk series datashee t usb device controller (usbd) 6.17 6.17.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device. it is compliant with usb 2.0 full - speed device specification and supports c ontrol/ b ulk/ i nterrupt/ i sochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controll er. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie . user needs to set the effective starting address of sram for each endpoint buffer through buffer segmentation register (usb d _bufsegx) . there are 8 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of e ndpoint c ontrol is also used to manage the data sequential synchronization, endpoint state, current start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the no - event - wake - up , device plu g - in or plug - out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usbd_intsts) to acknowle dge what kind of interrupt occurring, and then check the related usb endpoint status register (usbd_epsts) to acknowledge what kind of event occurring in this endpoint. a software - disconnect function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables se0 bit (usbd_se0), the usb controller will force the output of usb_d + and usb_d - to level low and its function is disabled. after disable the se0 bit, host will enumerate th is usb d evice again. for more information on the universal serial bus, please refer to universal serial bus specification revision 1.1. 6.17.2 features ? compliant with usb 2.0 full - speed specification ? provide s 1 interrupt vector with 4 different interrupt events ( nev wk, vbusdet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type s ? support s suspend function when no bus activity existing for 3 ms ? supports 8 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide s remote wake - up capability
m4 tk jan . 06 , 201 6 page 105 of 144 rev .1.00 m4tk series datashee t usb 1.1 host controller (usbh) 6.18 6.18.1 overview this chip is equip ped with a usb 1.1 host controller (usbh) that supports open host controller interface (openhci, ohci) specification, a register - level description of a host controller, to manage the devices and data transfer of universal serial bus (usb). the usbh supports an int egrated root hub with a usb port, a dma for real - time data transfer between system memory and usb bus, port power control and port over current detection. the usbh is responsible for detecting the connect and disconnect of usb devices, managing data transf er, collecting status and activity of usb bus, providing power control and detecting over current of attached usb devices. 6.18.2 features ? supports universal serial bus (usb) specification revision 1.1. ? supports open host controller interface (openhci) specifica tion revision 1.0. ? supports both full - speed (12mbps) and low - speed (1.5mbps) usb devices. ? supports control, bulk, interrupt and isochronous transfers. ? supports an integrated root hub. ? supports a usb host port shared with usb device (otg function). ? supports port power control and port over current detection. ? supports dma f or real - time data transfer .
m4 tk jan . 06 , 201 6 page 106 of 144 rev .1.00 m4tk series datashee t usb on - the - go (otg) 6.19 6.19.1 overview the otg controller interfaces to usb phy and usb controllers which consist of a usb 1.1 host controller and a usb 2.0 fs device controller. the otg controller supports hnp and srp protocols defined in the on - the - go and embedded host supplement to the usb 2.0 revision 1.3 specification. usb frame, including usb host, usb device, and otg controller, can be configured as host - only, device - only, id - dependent or otg device mode defined in usbrole (sys_usbphy[1:0]). in host - only mode , usb frame acts as usb host . usb frame can support both full - speed and low - speed transfer. in device - only mode , usb frame acts as usb device . usb frame onl y supports full - speed transfer. in id - dependent mode , usb frame can be usb host or usb device depend s on usb_ id pin state . in otg device mode, the role of usb frame depend s on the definition of otg specification. usb frame only supports full - speed transfer when otg device acts as a peripheral . 6.19.2 features ? built in usb phy ? configurable to operate as: ? host - only ? device - only ? id - dependent: the role of usb frame is only dependent on usb_id pin value -- as usb host (usb_id pin is low) or usb device (usb_id pin is high). not support hnp or srp protocol. ? otg device: dependent on usb_id pin status to be a - device (usb_id pin is low) or b - device (usb_id pin is high). support hnp and srp protocols.
m4 tk jan . 06 , 201 6 page 107 of 144 rev .1.00 m4tk series datashee t controller area network (can) 6.20 6.20.1 overview the c_can consists of the can core, message ram, message handler, control registers and module interface (refer to e` ! ??? ) the can core per forms communication according to the can protocol version 2.0 part a and b. the bit rate can be programmed to values up to 1mbit/s. for the connection to the physical layer, additional transceiver hardware is required. for communication on a can network, i ndividual message objects are configured. the message objects and identifier masks for acceptance filtering of received messages are stored in the message ram. all functions concerning the handling of messages are implemented in the message handler. these functions include acceptance filtering, the transfer of messages between the can core and the message ram, and the handling of transmission requests as well as the generation of the module interrupt. the register set of the c_can can be accessed directly b y the software through the module interface. these registers are used to control/configure the can core and the message handler and to access the message ram. 6.20.2 features ? supports can protocol version 2.0 part a and b ? bit rates up to 1 mbit/s ? 32 message obje cts ? each message object has its own identifier mask ? programmable fifo mode (concatenation of message objects) ? maskable interrupt ? disabled automatic re - transmission mode for time triggered can applications ? programmable loop - back mode for self - test operation ? 16 - bit module interfaces to the amba apb bus ? supports wake - up function
m4 tk jan . 06 , 201 6 page 108 of 144 rev .1.00 m4tk series datashee t touch key (tk) 6.21 6.21.1 overview the capacitive touch - key sensing controller supports several programmable sensitivity levels for different applications to detect the finger touched or near the electrode covered by dielectric. it supports up to 16 touch - keys with single - scan or programmable periodic key - scans, and system can be waked - up by any key for low power applications. 6.21.2 features ? supports up to 16 touch - keys. ? supports flexible reference channel setting, at least 1 reference channel needed. ? programmable sensitivity levels for each channel. ? programmable scanning speed for different applications. ? supports any touch - key wake - up for low - power applications. ? supports single key - scan a nd programmable periodic key - scan. ? programmable interrupt options for key - scan complete with or without threshold control.
m4 tk jan . 06 , 201 6 page 109 of 144 rev .1.00 m4tk series datashee t crc controller (crc) 6.22 6.22.1 overview the cyclic redundancy check (crc) generator can perform crc calculation with programmable polynomial settings. 6.22.2 features ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? programmable seed value ? supports programmable order reverse setting for input data and crc checksum ? supports programmable 1s complement setting for input data and crc checksum ? supports 8/16/32 - bit of data width ? 8 - bit write mode: 1 - ahb clock cycle operation ? 16 - bit write mode: 2 - ahb clock cycle operation ? 32 - bit write mode: 4 - ahb clock cycle operation ? supports using pdma to write data to perform crc operation
m4 tk jan . 06 , 201 6 page 110 of 144 rev .1.00 m4tk series datashee t enhanced 12 - bit analog - to - digital converter (eadc) 6.23 6.23.1 overview the m4tk series contains one 12 - bit successive approximation analog - to - digital converter (sar a/d converter) with 16 external input channels and 3 internal channels. the a/d converter can be started by software trigger , pwm0/1 triggers, timer0~3 overflow pulse tri ggers, adint0, adint1 interrupt eoc (end of conversion) pulse trigger and external pin (stadc) input signal. 6.23.2 features ? analog input voltage range: 0~ v ref (max to av dd ). ? reference voltage from v ref pin or av dd . ? 12 - bit resolution and 10 - bit accuracy is guaranteed. ? up to 16 single - end analog external input channels or 8 pair differential analog input channels . ? 3 internal channels, they are band - gap voltage (v bg ), temperature sensor (v temp ), and battery power (v bat ) ? four adc interrupts (adint0~3) with indi vidual interrupt vector addresses. ? maximum adc clock frequency is 20 mhz . ? up to 1 ms ps conversion rate. ? configurable adc internal sampling time. ? up to 19 sample modules ? each of sample module 0~15 which is configurable for adc converter channel eadc_ch0~15 and trigger source. ? sample module 16~18 is fixed for adc channel 16, 17, 18 input sources as band - gap voltage, temperature sensor, and battery power (v bat ). ? double buffer for sample module 0~3 ? c onfigurable sampling time for each sample module. ? conversion results are held in 1 9 data registers with valid and overrun indicators. ? an a/d conversion can be started by : ? w rite 1 to swtrg n (eadc_swtrg[n] , n = 0~1 8 ) ? external pin stadc ? timer0~3 overflow pu lse triggers ? adint0 and adint1 interrupt eoc (end of conversion) pulse triggers ? pwm triggers ? supports pdma transfer
m4 tk jan . 06 , 201 6 page 111 of 144 rev .1.00 m4tk series datashee t digital to analog converter (dac) 6.24 6.24.1 overview the dac module is a 12 - bit, voltage output digital - to - analog converter. it can be used in conjunction with the pdma controller. the dac integrates a voltage output buffer that can be used to reduce output impendence and drive external loads directly without having to add an external operational amplifier. 6.24.2 features ? analog output voltage range: 0~av dd . ? reference voltage from internal reference voltage (int_vref), v ref pin or av dd . ? dac maximum conversion updating rate 1m sps. ? supports voltage output buffer mode and bypass voltage output buffer mode. ? supports software and hardware trigger to start dac conversion. ? supports pdma request.
m4 tk jan . 06 , 201 6 page 112 of 144 rev .1.00 m4tk series datashee t analog comparator controller (acmp) 6.25 6.25.1 overview the m4tk contains two comparators. the comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. each comparator can be configured to generate an interrupt when the comparator output value changes. 6.25.2 features ? analo g input voltage range: 0 ~ a v dd (voltage of av dd pin) ? supports hysteresis function ? supports wake - up function ? selectable input sources of positive input and negative input ? acmp0 supports ? 4 positive sources ? acmp0_p0, acmp0_p1, acmp0_p2, or acmp0_p3 ? 4 negativ e sources ? acmp0_n ? comparator reference voltage (crv) ? internal band - gap voltage (v bg ) ? dac output (dac_out) ? acmp1 supports ? 4 positive sources ? acmp1_p0, acmp1_p1, acmp1_p2, or acmp1_p3 ? 4 negative sources ? acmp1_n ? comparator reference voltage (crv) ? internal band - gap voltage (v bg ) ? dac output (dac_out) ? shares one acmp interrupt vector for all comparators
m4 tk jan . 06 , 201 6 page 113 of 144 rev .1.00 m4tk series datashee t 7 application circuit a v s s a v d d a v c c d v c c v s s v d d 0 . 1 u f f b f b p o w e r c r y s t a l m 4 t k s e r i e s c d e v i c e l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f u a r t r x d t x d c a n t r a n s c e i v e r r c a n _ h c a n _ l o d b p o r t c a n c a n _ t x c a n _ r x d d v c c s m a r t c a r d s l o t s c _ p w r s c _ r s t s c _ c l k s c _ d a t s c _ d e t e c t d v c c 1 0 u f / 1 0 v 1 0 k n r s t 4 ~ 2 4 m h z c r y s t a l 2 0 p 2 0 p x t 1 _ o u t x t 1 _ i n v d d v s s i 2 c l k d i o i 2 c _ s d a i 2 c _ s c l 4 . 7 k d v c c 4 . 7 k d v c c v d d i o v b a t v d d v s s n r e s e t i c e _ c l k i c e _ d a t s w d i n t e r f a c e v r e f 3 2 . 7 6 8 k h z c r y s t a l 2 0 p 2 0 p x 3 2 _ o u t x 3 2 _ i n l d o c a p _ 1 u f r e s e t c i r c u i t v d d v s s s p i d e v i c e c s c l k m i s o s p i _ s s m o s i s p i _ c l k s p i _ m i s o s p i _ m o s i d v c c u s b o t g s l o t u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ i d u s b _ v b u s 1 u f
m4 tk jan . 06 , 201 6 page 114 of 144 rev .1.00 m4tk series datashee t 8 electrical character istics absolute maximum ratings 8.1 symbol parameter min max unit v dd ? v ss dc power supply - 0.3 +7.0 v v in input voltage v ss - 0.3 v dd + 0.3 v 1/t clcl oscillator frequency 4 20 mhz t a operating temperature - 40 +105 t st storage temperature - 55 +150 i dd maximum current into v dd - 120 ma i ss maximum current out of v ss 120 ma i io maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device.
m4 tk jan . 06 , 201 6 page 115 of 144 rev .1.00 m4tk series datashee t dc electrical characteristics 8.2 ( v dd - v ss = 2.5 ~ 5.5 v, t a = 25 ? c) p arameter symbol specification test condition s min . typ . max . un i t operation voltage v dd 2.5 - 5.5 v v dd = 2 .5 v ~ 5.5 v up to 72 mhz power supply for pe.8~pe.13 v dd io 1.8 - 5.5 v rtc operation voltage for pf.0~pf.2 v bat 2.5 - 5.5 v power ground v ss / av ss - 0.3 0 0.3 v ldo output voltage v ldo 1.62 1.8 1.98 v v dd 2.5 v band - gap voltage v bg 1.175 1.21 1.225 v v dd = 2 .5 v ~ 5.5 v , t a = 25 ? c allowed voltage difference for v dd and av dd v dd - av dd - 0.3 0 0.3 v operating current normal run mode hclk = 72 mhz while(1){} executed from flash i dd 1 - 64 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x v v i dd 2 - 32 - ma 5.5v 12 mhz x v x i dd 3 - 63 - ma 3.3v 12 mhz x v v i dd 4 - 31 - ma 3.3v 12 mhz x v x operating current normal run mode hclk = 50 mhz while(1){} executed from flash i dd 5 - 45 - ma 5.5v 12 mhz x v v i dd 6 - 23 - ma 5.5v 12 mhz x v x i dd 7 - 45 - ma 3.3v 12 mhz x v v i dd 8 - 22 - ma 3.3v 12 mhz x v x operating current normal run mode hclk =22.1184 mhz while(1){} executed from flash i dd 9 - 20 - ma 5.5v x v x v i dd 10 - 10 - ma 5.5v x v x x i dd 11 - 20 - ma 3.3v x v x v i dd 12 - 10 - ma 3.3v x v x x operating current normal run mode hclk = 12 m h z while(1){} executed from flash i dd 13 - 12 - ma 5.5v 12 mhz x x v i dd1 4 - 6 - ma 5.5v 12 mhz x x x i dd1 5 - 12 - ma 3.3v 12 mhz x x v i dd1 6 - 6 - ma 3.3v 12 mhz x x x operating current normal run mode i dd1 7 - 3.4 - ma 5.5v 12 mhz x x v i dd1 8 - 1.9 - ma 5.5v 12 mhz x x x
m4 tk jan . 06 , 201 6 page 116 of 144 rev .1.00 m4tk series datashee t p arameter symbol specification test condition s min . typ . max . un i t hclk =4 mhz while(1){} executed from flash i dd1 9 - 3.3 - ma 3.3v 12 mhz x x v i dd 20 - 1.8 - ma 3.3v 12 mhz x x x operating current hclk = 32.768 k hz while(1){} executed from flash i dd 21 - 153 - u a v dd l xt (khz) hirc pll all digital modules 5.5v 32.768 x x v i dd 22 139 u a 5.5v 32.768 x x x i dd 23 133 u a 3.3v 32.768 x x v i dd 24 - 120 - u a 3.3v 32.768 x x x operating current normal run mode hclk = 10 kh z while(1){} executed from flash i dd 25 - 134 - a v dd hxt /l xt l irc (khz) pll all digital modules 5.5v x 10 x v i dd 26 - 130 - a 5.5v x 10 x x i dd 27 - 121 - a 3.3v x 10 x v i dd 28 - 117 - a 3.3v x 10 x x operating current idle mode hclk = 72 m h z i idle1 - 42 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x v v i idle2 - 9 - ma 5.5v 12 mhz x v x i idle3 - 42 - ma 3.3v 12 mhz x v v i idle4 - 8 - ma 3.3v 12 mhz x v x operating current idle mode hclk = 50 m h z i idle 5 - 30 - ma 5.5v 12 mhz x v v i idle 6 - 6 - ma 5.5v 12 mhz x v x i idle 7 - 30 - ma 3.3v 12 mhz x v v i idle 8 - 6 - ma 3.3v 12 mhz x v x operating current idle mode hclk =22.1184 mhz i idle 9 - 12 - ma 5.5v x v x v i idle 10 - 3 - ma 5.5v x v x x i idle 11 - 12 - ma 3.3v x v x v i idle 12 - 3 - ma 3.3v x v x x operating current idle mode hclk =12 mhz i idle 13 - 8 - ma 5.5v 12 mhz x x v i idle1 4 2 ma 5.5v 12 mhz x x x i idle1 5 - 8 - ma 3.3v 12 mhz x x v i idle1 6 - 2 - ma 3.3v 12 mhz x x x operating current i idle1 7 - 2.5 - ma 5.5v 12 mhz x x v
m4 tk jan . 06 , 201 6 page 117 of 144 rev .1.00 m4tk series datashee t p arameter symbol specification test condition s min . typ . max . un i t idle mode hclk =4 mhz i idle18 - 0.9 - ma 5.5v 12 mhz x x x i idle1 9 - 2.4 - ma 3.3v 12 mhz x x v i idle 20 - 0.8 - ma 3.3v 12 mhz x x x operating current idle mode 32.768 k hz i idle 21 - 143 - u a v dd l xt (khz) hirc pll all digital modules 5.5v 32.768 x x v i idle 22 - 128 - u a 5.5v 32.768 x x x i idle 23 130 u a 3.3v 32.768 x x v i idle 24 115 u a 3.3v 32.768 x x x operating current idle mode at 10 khz i idle 25 - 131 - u a v dd hxt /l xt l irc (khz) pll all digital modules 5.5v x 10 x v i idle 26 - 127 - a 5.5v x 10 x x i idle 27 - 118 - a 3.3v x 10 x v i idle 28 - 113 - a 3.3v x 10 x x standby current power - down mode (deep sleep mode) i pwd1 20 ? a v dd hxt/hi rc/pll lxt (khz) rtc ram retension 5.5v x x x v i pwd 2 22 ? a 5.5v x 32.768 v v i pwd 3 18 ? a 3.3v x x x v i pwd 4 20 ? a 3.3v x 32.768 v v rtc operating current i vbat 1.7 1.9 8.1 u a v bat = 5.0 v, 32.768 khz external low speed crystal oscillator (lxt) , rtc on and v dd /a v dd power domain off. 1.6 1.8 7.7 u a v bat = 3.0 v, 32.768 khz external low speed crystal oscillator (lxt) , rtc on and v dd /a v dd power domain off. input current at /reset [1] i in - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v logic 0 i nput current (quasi - bidirectional mode) i il - - 67 - 75 ? a v dd = v dd io = v bat = 5.5 v, v in = 0v logic 1 to 0 transition current (quasi - bidirectional mode) [* 3 ] i tl - - 610 - 650 ? a v dd = v dd io = v bat = 5.5 v, v in = 2. 0v input leakage current i lk - 1 - +1 ? a v dd = v dd io = v bat = 5.5 v, 0 < v in < v dd open - drain or input only mode
m4 tk jan . 06 , 201 6 page 118 of 144 rev .1.00 m4tk series datashee t p arameter symbol specification test condition s min . typ . max . un i t input low voltage (ttl input) v il1 - 0.3 - 0.8 v v dd = v dd io = v bat = 4.5 v - 0.3 - 0.6 v dd = v dd io = v bat = 2.5 v input low voltage (ttl input for pe8 ~ pe13 ) v il 2 - 0.3 - 0.3 v v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v input high voltage (ttl input) v ih1 2.0 - v dd + 0. 3 v v dd = v dd io = v bat = 5.5 v 1.5 - v dd + 0. 3 v dd = v dd io = v bat = 3.0 v input high voltage (ttl input for pe8 ~ pe13 ) v ih 2 1. 0 - v dd io + 0. 3 v v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v hysteresis voltage of pa , pb, pc, pd,pe, pf (schmitt input) v hy 0.2v dd v input low voltage xt1[*2] v il3 0 - 0.8 v v dd = 4.5 v 0 - 0.4 v dd = 2.5 v input high voltage xt1[*2] v ih3 3.5 - v dd + 0.3 v v dd = 5.5 v 2.4 - v dd + 0.3 v dd = 3.0 v x32 output pin v xout 0.6 0.9 v input low voltage x32i [*4] v il 4 0 - v xout - 0.3 v input high voltage x32 i[*4] v ih 4 v xout +0.3 1.8 v negative going threshold (schmitt input), n rst v il 5 - 0.3 - 0.2 v dd v positive going threshold (schmitt input), n rst v ih 5 0.7 v dd - v dd + 0.3 v internal n r e s e t pin pull up resistor r rst 40 150 k input low voltage ( schmitt input ) v il 6 - 0. 3 - 0.3 v dd v v dd = v dd io = v bat = 2. 5 ~ 5 .5 v input low voltage (schmitt input for pe8~ pe13 ) v il 7 - 0. 3 - 0.3 v dd io v v dd io = 1.8 v ~ 5.5v input high voltage (schmitt input) v ih 6 0.7 v dd - v dd + 0. 3 v v dd = v dd io = v bat = 2. 5 ~ 5 .5 v
m4 tk jan . 06 , 201 6 page 119 of 144 rev .1.00 m4tk series datashee t p arameter symbol specification test condition s min . typ . max . un i t input low voltage (schmitt input for pe8~ pe13 ) v ih 7 0.7 v dd io - v dd io + 0. 3 v v dd io = 1.8 v ~ 5.5v source current (quasi - bidirectional mode) i sr11 - 300 - 400 - ? a v dd = v dd io = v bat = 4.5 v, v s = 2.4 v i sr12 - 50 - 80 - ? a v dd = v dd io = v bat = 2.7 v, v s = 2.2 v i sr13 - 40 - 73 - ? a v dd = v dd io = v bat = 2.5 v, v s = 2.0 v source current (quasi - bidirectional mode for pe8~ pe13 ) i sr1 4 - 11 - 19 ? a v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v, v s = 1.6 v source current (push - pull mode) i sr21 - 20 - 26 - ma v dd = v dd io = v bat = 4.5 v, v s = 2.4 v i sr22 - 3 - 5.2 - ma v dd = v dd io = v bat = 2.7 v, v s = 2.2 v i sr23 - 2.5 - 5 - ma v dd = v dd io = v bat = 2.5 v, v s = 2.0 v source current (set io as push - pull mode and basic driving strength only for pe8~pe13) i sr2 4 - 1 - 1.5 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v, v s = 1.6 v source current (set io as push - pull mode and high driving strength only for pe8~pe13) i sr 31 - 28 - 47 - ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 4.5 v, v s = 2.4 v i sr 32 - 5.3 - 8.8 - ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 2 . 7 v, v s = 2.2 v i sr 33 - 4.9 - 8.1 - ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 2 .5 v, v s = 2.0 v i sr 34 - 1 . 5 - 2.5 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v, v s = 1.6 v sink current (quasi - bidirectional , open - drain and push - pull mode) i sk11 10 17 - ma v dd = v dd io = v bat = 4.5 v, v s = 0.45 v i sk12 6 11 - ma v dd = v dd io = v bat = 2.7 v, v s = 0.45 v i sk13 5 10 - ma v dd = v dd io = v bat = 2.5 v, v s = 0.45 v sink current (only for pe8~pe13) i sk1 4 3.6 6 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v, v s = 0.45 v sink current (set io as high driving strength only for pe8~pe13) i sk 21 14.7 24.5 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 4.5 v, v s = 0.45 v i sk 22 9.2 15.3 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 2.7 v, v s = 0.45 v i sk 23 8.5 14.1 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 2.5 v, v s = 0.45 v
m4 tk jan . 06 , 201 6 page 120 of 144 rev .1.00 m4tk series datashee t p arameter symbol specification test condition s min . typ . max . un i t i sk 24 5.4 9 ma v dd = v bat = 2. 5 ~ 5 .5 v v dd io = 1.8 v, v s = 0.45 v notes: 1. nr e s e t pin is a schmitt trigger input. 2. xt1_in is a cmos input. 3. all p ins can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5v, t he transition current reaches its maximum value when v in approximates to 2v. 4. if x32i is as external clock input, the input high voltage should be lower than 1.8v to avoid chip damage .
m4 tk jan . 06 , 201 6 page 121 of 144 rev .1.00 m4tk series datashee t ac electrical characteristics 8.3 8.3.1 external 4~24 mhz high speed c rystal (hxt) input clock symbol p arameter m in t yp max un i t test condition s t chcx clock high time 10 - - ns - t clcx clock low time 10 - - ns - t clch clock rise time 2 - 15 ns - t chcl clock fall time 2 - 15 ns - v ih input high voltage 0.7v dd v dd v - v il input low voltage 0 0.3v dd v - 8.3.2 external 4~2 0 mhz high speed crystal (hxt) oscillator symbol parameter min . typ . max unit test cond i tion s v hxt operation voltage 2.5 - 5.5 v - t a temperature - 40 - 105 - i hxt operating c urrent - 2 - ma 12 mhz , v dd = 5 .5 v - 0.8 - ma 12 mhz , v dd = 3.3 v f hxt c lock f requency 4 - 2 0 mhz - typical crystal application circuits 8.3.2.1 c rystal c1 c 2 4 mhz ~ 2 0 mhz 10~20 pf 10~20 pf t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l v i l v i h n o t e : d u t y c y c l e i s 5 0 % .
m4 tk jan . 06 , 201 6 page 122 of 144 rev .1.00 m4tk series datashee t figure 8.3 - 1 typical crystal application circuit 8.3.3 22.1184 mhz i nternal h igh s peed rc o scillator (hirc) s ymbol parameter min typ max unit test condition s v hrc supply voltage 1.62 1.8 1.98 v - f hrc center frequency - 22. 1184 mhz - calibrated internal oscillator frequency - 1 - + 1 % t a = 25 , v dd = 5 v - 2 - + 2 % t a = - 40 ~ 105 v dd = 2. 5 v ~ 5 .5 v i hrc operating c urrent - 790 - a t a = 25 , v dd = 5 v note: number of test samples : 10 . figure 8.3 - 2 hirc a ccuracy vs. t emperature -1.40% -1.20% -1.00% -0.80% -0.60% -0.40% -0.20% 0.00% 0.20% 0.40% 0.60% 0.80% -50 0 50 100 150 deviation percentage % ta hirc oscillator accuracy vs. temperature max min x t a l 1 c 1 c 2 x t a l 2 4 ~ 2 0 m h z c r y s t a l v s s v s s
m4 tk jan . 06 , 201 6 page 123 of 144 rev .1.00 m4tk series datashee t 8.3.4 32.768 kh z external l ow s peed crystal (lxt) i nput clock symbol p arameter m in t yp max un i t test condition s t chcx clock high time tbd - - ns - t clcx clock low time tbd - - ns - t clch clock rise time tbd - tbd ns - t chcl clock fall time tbd - tbd ns - xin_ v ih lxt input pin input high voltage xout+0.3 1.8 v - xin_ v il lxt input pin input low voltage 0 xout - 0.3 v - xout lxt output pin 0.6 0.9 v 8.3.5 32.768 khz external low speed crystal (lxt) oscillator parameter condition min. typ. max. unit operation voltage v bat - 2. 5 - 5.5 v operation temperature - - 40 - 105 operation current 32.768khz at v bat =5v 1.6 ? a c lock f requency external crystal - 32 .768 - khz lxt typical crystal application circuits 8.3.5.1 crystal c 1 c 2 32.768 khz 10~20 pf 10~20 pf t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l x i n _ v i l x i n _ v i h n o t e : d u t y c y c l e i s 5 0 % .
m4 tk jan . 06 , 201 6 page 124 of 144 rev .1.00 m4tk series datashee t figure 8.3 - 3 typical crystal application circuit 8.3.6 10 khz i nternal l ow s peed rc o scillator (lirc) symbol parameter min typ max unit test condition s v lrc supply v oltage 2. 5 - 5.5 v - f lrc center frequency - 10 - k hz - oscillator frequency - 3 0 - + 3 0 % v dd = 2. 5 v ~ 5.5 v t a = 25 - 50 - + 50 % v dd = 2. 5 v ~ 5.5 v t a = - 40 ~ + 105 x 3 2 _ i n c 1 c 2 x 3 2 _ o u t c r y s t a l v s s v s s
m4 tk jan . 06 , 201 6 page 125 of 144 rev .1.00 m4tk series datashee t analog characteristics 8.4 8.4.1 12 - bit sar adc symbol parameter min typ max unit test c ondition - resolution 12 bit - dnl differential n onlinearity e rror - - 2 lsb - inl integral n onlinearity e rror - - 2 lsb - e o offset e rror - 3 - lsb - e g gain e rror (transfer g ain) - - 3 - lsb - e a absolute e rror - 4 - lsb - - monotonic guaranteed - - f adc adc c lock f requency - - 21 mhz a v dd = 4.5~5. 5 v - - 8.4 a v dd = 2.5~5.5 v f s sample r ate (f adc /t conv ) - - 1000 ksps a v dd = 4. 5 ~5.5 v t conv = 21 clock f adc = 21 mhz - - 400 ksps a v dd = 2. 5 ~5.5 v t conv = 21 clock f adc = 8.4 mhz t acq acquisition t ime (sample s tage) 2~9 1/f adc default: 6 ( 1/f adc ) eadc_sctlx[31:24]=0 t conv total c onversion t ime 16~23 1/f adc t conv = t acq + 1 5 default: 21 ( 1/f adc ) eadc_sctlx[31:24]=0 a v dd #1 supply v oltage 2.5 - 5.5 v - i dda #1 supply c urrent (avg.) - 2. 8 - ma a v dd = 5 v v in #1 analog input v oltage 0 - v ref v - v ref reference v oltage 2.5 - a v dd v a v dd = 5 v c in #1 input c apacitance - 6 - pf - r in #1 input load - 6.5 - k - note: #1: design by guarantee, no test in production.
m4 tk jan . 06 , 201 6 page 126 of 144 rev .1.00 m4tk series datashee t note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. typical c onnection diagram using the adc figure 8.4 - 1 typical connection diagram using the adc (1) refer to adc spec for the values of r in , c in 1 2 3 4 5 6 4 0 9 5 4 0 9 4 7 4 0 9 3 4 0 9 2 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 4 0 9 5 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b v d d 1 2 - b i t c o n v e r t e r a i n x r i n c i n ( 1 ) ( 1 )
m4 tk jan . 06 , 201 6 page 127 of 144 rev .1.00 m4tk series datashee t 8.4.2 ldo s ymbol parameter min typ max unit test condition vdd dc power supply 2.5 - 5.5 v - vldo output voltage 1.62 1.8 1.98 v - ta temperature - 40 25 105 notes: 1. it is recommended a 0.1f bypass capacitor is connected between v dd and the closest v ss pin of the device. 2. for ensuring power stability, a 1f capacitor must be connected between ldo _cap pin and the closest v ss pin of the device. 8.4.3 low voltage reset s ymbol parameter min typ max unit test condition a v dd supply voltage 0 - 5.5 v - t a temperature - 40 25 105 - i lvr quiescent current - 1 5 a a v dd = 5.5 v v lvr threshold v oltage 2.00 2.20 2.45 v t a = 10 5 1. 90 2.0 0 2. 10 v t a = 25 1.70 1.90 2.10 v t a = - 40 8.4.4 brown - out detector symbol parameter min typ max unit test condition a v dd supply voltage 0 - 5.5 v - t a temperature - 40 25 105 - i bod quiescent c urrent - - 1 40 a av dd = 5.5 v v bod brown - o ut v oltage (falling edge) 4.2 4.4 4.6 v bov_vl [1:0] = 11 3.5 3.7 3.9 v bov_vl [1:0] = 10 2.55 2.7 2.85 v bov_vl [1:0] = 01 2.05 2.2 2.35 v bov_vl [1:0] = 00 v bod brown - o ut v oltage (rising edge) 4.3 4.5 4.7 v bov_vl [1:0] = 11 3.6 3.8 4.0 v bov_vl [1:0] = 10 2.6 2.75 2.9 v bov_vl [1:0] = 01 2.1 2.25 2.4 v bov_vl [1:0] = 00 8.4.5 power - on reset symbol parameter min typ max unit test condition
m4 tk jan . 06 , 201 6 page 128 of 144 rev .1.00 m4tk series datashee t t a temperature - 40 25 105 - v por reset v oltage 1.6 2 2.4 v - v por vdd start voltage to ensu r e power - on reset - - 100 mv rr vdd vdd raising rate to ensu r e power - on reset 0. 025 - - v/ms t por minimum time for vdd stays at vpor to ensu r e power - on reset 0.5 - - ms figure 8.4 - 2 power - up ramp condition 8.4.6 temperature sensor symbol p arameter m in t yp m ax u nit test condition t a temperature - 40 - 105 i temp current c onsumption - 16 - a - gain - 1. 55 - 1.672 - 1. 75 mv/ - offset 7 35 748 7 55 mv t a = 0 note: 1. the temperature sensor formula for the output voltage (vtemp) is as below equation. 2. vtemp (mv) = gain (mv/ ) x temperature ( ) + offset (mv) t p o r r r v d d v p o r v d d t i m e
m4 tk jan . 06 , 201 6 page 129 of 144 rev .1.00 m4tk series datashee t 8.4.7 comparator symbol p arameter m in typ m ax u nit test condition v cmp supply voltage 2.5 - 5.5 v t a temperature - 40 25 105 - i cmp operation c urrent - 35 70 a a v dd = 5 v v off input o ffset v oltage 10 mv a v dd = 5 v v sw output s wing 0.1 - a v dd - 0.1 v - v com input c ommon m ode r ange 0.1 - a v dd C 0.1 v - - dc g ain 40 70 * - db - t pgd propagation d elay - 125 - ns v cm = 1.2 v , v diff = 0.1 v v hys hysteresis - 40 60 mv a v dd = 5 v t stb stable time - 0.26 1 s a v dd = 5 v note: * guaranteed by design, not tested in production. 8.4.8 12 - bit d a c symbol p arameter m in typ m ax u nit test condition av dd analog supply voltage 2.5 - 5.5 v n r resolution 12 bit v ref reference supply voltage 2.5 - av dd v dnl differential non - linearity error - 0.5 - 1 lsb 10 - bit, buffer off - 0.5 - 2.5 12 - bit, buffer off inl integral non - linearity error - - 1 lsb 10 - bit, buffer off - - 2.5 12 - bit, buffer off oe offset error - - +1 lsb 10 - bit, buffer off - - +2 12 - bit, buffer off ge gain error - - - 2 lsb 10 - bit, buffer off - - - 8 12 - bit, buffer off ae absolute error - - - 2 lsb 10 - bit, buffer off - - - 8 12 - bit, buffer off - monotonic 10 - bit g uaranteed v o output voltage 0.1 v ref C 0.15 v buffer on r load resistive load 7.5 - - k buffer on r o output impedance - 8.2 22.5 k c load capacitive load - - 20 pf buffer off
m4 tk jan . 06 , 201 6 page 130 of 144 rev .1.00 m4tk series datashee t - -- 50 buffer on i dda analog supply current - - 350 ua av dd = 5.5v, buffer on i ref reference supply current - - 260 ua v ref = 5.5v t stab settling time - 4 8 us t ransition between the lowest and the highest input codes when v o reaches final value 1 lsb f s update rate - - 1 msps t ransition between a djacent codes t wakeup wake - up time - - 10 us 8.4.9 internal voltage reference symbol parameter min. typ. max. unit test condition v vref a v dd 2. 5 5.5 v - v ref1 vref(2.56v) 2.483 2.560 2.637 v av dd >= 2.9v v ref2 vref(2.048v) 1.986 2.048 2.109 v av dd >= 2. 5 v v ref3 vref(3.072v) 2.98 3.072 3.164 v av dd >= 3.4v v ref4 vref(4.096v) 3.973 4.096 4.219 v av dd >= 4.5v 8.4.10 usb phy low - full - speed dc electrical specifications 8.4.10.1 symbol parameter min. typ. max. unit test conditions v ih input h igh (driven) 2.0 - v - v il input l ow - - 0.8 v - v di differential i nput s ensitivity 0.2 - v |padp - padm| v cm differential c ommon - mode r ange 0.8 - 2.5 v includes v di range v se single - ended r eceiver t hreshold 0.8 - 2.0 v - receiver h ysteresis - 200 mv - v ol output l ow (driven) 0 - 0.3 v - v oh output h igh (driven) 2.8 - 3.6 v - v crs output s ignal c ross v oltage 1.3 - 2.0 v - r pu pull - up r esistor 1.425 - 1.575 k - z drv driver o utput r esistance - 10 - steady state drive* c in transceiver c apacitance - - 20 pf pin to gnd *driver output resistance doesnt include series resistor resistance.
m4 tk jan . 06 , 201 6 page 131 of 144 rev .1.00 m4tk series datashee t usb full - speed driver electrical characteristics 8.4.10.2 symbol parameter min. typ. max. unit test conditions t fr rise time 4 - 20 ns c l =50p t ff fall time 4 - 20 ns c l =50p t frff rise and f all t ime m atching 90 - 111.11 % t frff =t fr /t ff usb ldo specification 8.4.10.3 symbol parameter min. typ. max. unit test conditions v bus v bus pin input voltage 4.0 5.0 5.5 v - v dd33 ldo output voltage 2.97 3.3 3.63 v - c bp external bypass capacitor - 1.0 - uf -
m4 tk jan . 06 , 201 6 page 132 of 144 rev .1.00 m4tk series datashee t flash dc electrical characteristics 8.5 symbol parameter min typ max unit test condition v fla [2] supply voltage 1.62 1.8 1.98 v t a = 2 5 n endur endurance 20,000 - cycles [1] t ret data retention 100 - - year t erase page erase time 20 - ms t prog program time 6 0 - us i dd1 read current - - 13.5 ma i dd2 program current - 10 - ma i dd3 erase current - 12 - ma notes: 1. number of program/erase cycles. 2. v fla is source from chip ldo output voltage.
m4 tk jan . 06 , 201 6 page 133 of 144 rev .1.00 m4tk series datashee t i 2 c dynamic characteristics 8.6 symbol parameter standard m ode [1] [ 2] fast m ode [1] [ 2] unit min . max . min . max . t low scl low period 4.7 - 1.2 - us t high scl high period 4 - 0.6 - us t su; sta repeated start condition setup time 4.7 - 1.2 - us t hd; sta start condition hold time 4 - 0.6 - us t su; sto stop condition setup time 4 - 0.6 - us t buf bus free time 4.7 [3] - 1.2 [3] - us t su;dat data setup time 250 - 100 - ns t hd;dat data hold time 0 [4] 3.45 [5] 0 [4] 0.8 [5] us t r scl/sda rise time - 1000 20+0.1cb 300 ns t f scl/sda fall time - 300 - 300 ns c b capacitive load for each bus line - 400 - 400 pf notes : 1. guaranteed by design, not tested in production. 2. hclk must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 8 mhz to achieve the maximum fast mode i 2 c frequency. 3. i 2 c controller must be retriggered immediately at slave mode after receiving stop condition. 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 5. the maximum hold time of the start condition has only to be met if the interface does not st retch the low period of scl signal. figure 8.6 - 1 i 2 c timing diagram t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
m4 tk jan . 06 , 201 6 page 134 of 144 rev .1.00 m4tk series datashee t spi dynamic characteristics 8.7 8.7.1 dynamic characteristics of data input and output pin symbol parameter min . typ . max . unit spi m aster m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t w(sckh) t w(sckl) spi high and low time, peripheral clock = 20mhz 22.5 - 27.5 ns t ds data input setup time 2 - - ns t h (mi) data input hold time 4 - - ns t v data output valid time - - 1 ns t h(mo) data output hold time 0 - - ns spi m aster m ode (vdd = 3 . 0~3.6 v, 30 pf loading capacitor ) t w(sckh) t w(sckl) spi high and low time, peripheral clock = 20mhz 22.5 - 27.5 ns t ds data input setup time 2 ns t h (mi) data input hold time 4 ns t v data output valid time - 1 ns t h(mo) data output hold time 0 - - ns figure 8.7 - 1 spi master mode timing diagram s p i c l o c k s p i d a t a i n p u t ( s p i _ m i s o ) s p i d a t a o u t p u t ( s p i _ m o s i ) c l k p o l = 0 t x n e g = 1 r x n e g = 0 c l k p o l = 1 t x n e g = 0 r x n e g = 1 t v d a t a v a l i d d a t a v a l i d t d s t d h s p i c l o c k s p i d a t a i n p u t ( s p i _ m i s o ) s p i d a t a o u t p u t ( s p i _ m o s i ) d a t a v a l i d c l k p o l = 0 t x n e g = 0 r x n e g = 1 c l k p o l = 1 t x n e g = 1 r x n e g = 0 t v d a t a v a l i d d a t a v a l i d d a t a v a l i d t d s t d h d a t a v a l i d d a t a v a l i d t f ( s c k ) t r ( s c k )
m4 tk jan . 06 , 201 6 page 135 of 144 rev .1.00 m4tk series datashee t symbol parameter min . typ . max . unit spi s lave m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t ss slave select setup time 3 - - p eripheral clock t sh slave select hold time 2 - - p eripheral clock t ds data input setup time 2 - - ns t h(si) data input hold time 5.5 - - ns t a(so) data output access time - - 18 ns t v data output valid time - 18.5 - 24.5 ns t h(so) data output hold time 6 - - ns spi s lave m ode (vdd = 3 . 0 v ~ 3 . 6 v, 30 pf loading capacitor ) t ss slave select setup time 3 - - p eripheral clock t sh slave select hold time 2 - - p eripheral clock t ds data input setup time 2 - - ns t h (si) data input hold time 6 - - ns t a(so) data output access time - - 24 ns t v data output valid time - 23 30 ns t h (so) data output hold time 7 - - ns
m4 tk jan . 06 , 201 6 page 136 of 144 rev .1.00 m4tk series datashee t figure 8.7 - 2 spi slave mode timing diagram s p i c l o c k s p i d a t a i n p u t ( s p i _ m o s i ) s p i d a t a o u t p u t ( s p i _ m i s o ) d a t a v a l i d c l k p o l = 0 t x n e g = 1 r x n e g = 0 c l k p o l = 1 t x n e g = 0 r x n e g = 1 t v d a t a v a l i d d a t a v a l i d d a t a v a l i d t d s t d h t s h t s s s p i s s s p i c l o c k s p i d a t a i n p u t ( s p i _ m o s i ) s p i d a t a o u t p u t ( s p i _ m i s o ) d a t a v a l i d c l k p o l = 0 t x n e g = 0 r x n e g = 1 c l k p o l = 1 t x n e g = 1 r x n e g = 0 t v d a t a v a l i d d a t a v a l i d d a t a v a l i d t d s t d h t s h t s s s p i s s s s a c t p o l = 1 s s a c t p o l = 0 s s a c t p o l = 1 s s a c t p o l = 0 t a ( s o )
m4 tk jan . 06 , 201 6 page 137 of 144 rev .1.00 m4tk series datashee t i 2 s dynamic characteristics 8.8 symbol parameter min max unit test conditions t w(ckh) i 2 s clock high time 42 - ns master f pclk = mhz, data: 24 bits, audio frequency = 256 khz t w(ckl) i 2 s clock low time 37 - t v (ws) ws valid time 7 - master mode t h(ws) ws hold time 1 - master mode t su(ws) ws setup time 34 - slave mode t h(ws) ws hold time 0 - slave mode ducy (sck) i 2 s slave input clock duty cycle 25 75 % slave mode t su(sd_mr) data input setup time 0 - ns master receiver t su(sd_sr) 0 - slave receiver t h(sd_mr) data input hold time 0 - master receiver t h(sd_sr) 0 - slave receiver t v(sd_st) data output valid time - 32 slave transmitter (after enable edge) t h(sd_st) data output hold time 16 - slave transmitter (after enable edge) t v(sd_mt) data output valid time - 5 master transmitter (after enable edge) t h(sd_mt) data output hold time 0 - master transmitter (after enable edge)
m4 tk jan . 06 , 201 6 page 138 of 144 rev .1.00 m4tk series datashee t figure 8.8 - 1 i 2 s master mode timing diagram figure 8.8 - 2 i 2 s slave mode timing diagram t w ( c k h ) t w ( c k l ) t h ( w s ) t v ( w s ) t h ( s d _ s t ) l s b t r a n s m i t ( 2 ) m s b t r a n s m i t b i t n t r a n s m i t l s b t r a n s m i t l s b r e c e i v e ( 2 ) m s b r e c e i v e b i t n r e c e i v e l s b r e c e i v e t s u ( s d _ m r ) t h ( s d _ m r ) s d t r a n s m i t s d r e c e i v e w s o u t p u t c p o l = 1 c p o l = 0 t v ( s d _ s t ) c k o u t p u t t w ( c k h ) t w ( c k l ) t h ( w s ) t s u ( w s ) t h ( s d _ s t ) l s b t r a n s m i t ( 2 ) m s b t r a n s m i t b i t n t r a n s m i t l s b t r a n s m i t l s b r e c e i v e ( 2 ) m s b r e c e i v e b i t n r e c e i v e l s b r e c e i v e t s u ( s d _ s r ) t h ( s d _ s r ) s d t r a n s m i t s d r e c e i v e w s i n p u t c p o l = 1 c p o l = 0 t v ( s d _ s t ) c k i n p u t
m4 tk jan . 06 , 201 6 page 139 of 144 rev .1.00 m4tk series datashee t 9 package dimensions lqfp 100l (14x14x1.4 mm f ootprint 2.0 mm) 9.1
m4 tk jan . 06 , 201 6 page 140 of 144 rev .1.00 m4tk series datashee t lqfp 64l (10x10x1.4 mm footprint 2.0 mm) 9.2
m4 tk jan . 06 , 201 6 page 141 of 144 rev .1.00 m4tk series datashee t lqfp 64l ( 7 x 7 x1.4 mm footprint 2.0 mm) 9.3
m4 tk jan . 06 , 201 6 page 142 of 144 rev .1.00 m4tk series datashee t lqfp 48l (7x7x1.4mm f ootprint 2.0mm) 9.4 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
m4 tk jan . 06 , 201 6 page 143 of 144 rev .1.00 m4tk series datashee t 10 revision history date revision description 201 6 . 01 . 0 6 1.0 0 preliminary v ersion .
m4 tk jan . 06 , 201 6 page 144 of 144 rev .1.00 m4tk series datashee t important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usage inclu des, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, al l types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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